The 8V19N850 is a fully integrated Radio Unit Clock Synchronizer and Jitter Attenuator designed as a high-performance clock solution for phase/frequency synchronization and signal conditioning of wireless base station radio equipment. The device supports JESD204B/C subclass 0 and 1 device clocks and SYSREF synchronization for converters. The 8V19N850 supports two independent frequency domains: one that can be used for the digital clock (Ethernet and FEC rates) domain with four outputs, and the device clock (RF-PLL) domain with 12 outputs. The Ethernet domain generates frequencies from two independent APLLs for flexibility; the outputs of the RF clock domain generate very low phase noise clocks for ADC/DAC circuits.

From the integrated RF-PLL, the device supports the clock generation of high-frequency device clocks for driving ADC/DAC devices low-frequency synchronization signals (SYSREF). A dual DPLL front-end architecture supports any frequency translation. Each DPLL provides a programmable bandwidth and a DCO function for real-time frequency/phase adjustments. The DPLLs can lock on 1PPS input signals and establish lock within 100s or less. Frequency information can be applied from DPLL-0 to DPLL-1 and vice versa to enable the combining of the frequency characteristics of two references (combo-mode). The 8V19N850 is configured through a pin-mapped I3C (including legacy I2C) and 3/4-wire SPI interface. I2C with master capabilities reads a default configuration from an external ROM device. GPIO ports can be configured for reporting and controlling purposes.


  • Device clock domain (RF-PLL) with support for JESD204B/C
  • Digital clock domain (Ethernet, FEC) with support for eEEC and T-BC/T-TSC Class C
  • 2 differential clock reference inputs with 1PPS (1Hz) to 1GHz input frequency
  • Dual DPLL front-end with independent clock paths
    • External control of the DCO for IEEE1588
    • Digital holdover with a 1.1 × 10-7 ppb accuracy
    • Programmable DPLL loop bandwidth 1mHz - 6kHz
    • Configurable phase delay (range: 1UI)
    • Hitless input switching with < 1ns output phase error
  • Reference monitors for input LOS, activity and frequency
  • 1 external synchronization input for JESD204B/C (LVCMOS)
  • 16 differential outputs
  • Optimized for low phase noise: -146dBc/Hz (1MHz offset; 245.76MHz clock)
  • Supply voltage (core): 3.3V; (outputs): 3.3V, 2.5V, and 1.8V
  • Board temperature range: -40°C to +105°C
  • Applicable Standards
    • ITU-T G.8262 EEC1/2, G.8262.1 eEEC
    • ITU-T G.8273.2 T-BC/T-TSC Class C
    • JESD204B and C


  • Wireless infrastructure 5G radio


Title language Type Format File Size Date
Datasheets & Errata
star 8V19N850D Datasheet Datasheet PDF 1.77 MB
User Guides & Manuals
8V19N850 Evaluation Board Manual Manual - Development Tools PDF 2.66 MB
8V19N850 Hardware Design Guide Guide PDF 401 KB
Application Notes & White Papers
8V19N850 Sysref Phase Deterministic and Phase Align Application Note PDF 261 KB
Frequency Control Word Setting Procedure for 8V19N850D Application Note PDF 41 KB
AN-807 Recommended Crystal Oscillators for Network Synchronization Application Note PDF 148 KB
AN-842 Thermal Considerations in Package Design and Selection Application Note PDF 495 KB
AN-838 Peak-to-Peak Jitter Calculations Application Note PDF 115 KB
AN-839 RMS Phase Jitter Application Note PDF 233 KB
AN-815 Understanding Jitter Units Application Note PDF 565 KB
AN-827 Application Relevance of Clock Jitter Application Note PDF 1.15 MB
AN-805 Recommended Ferrite Beads Application Note PDF 121 KB
AN-806 Power Supply Noise Rejection Application Note PDF 438 KB
8V19N850D ITU-T G.8262 and G.8262.1 Compliance Test Report Report PDF 2.55 MB
RF Timing Family Product Overview Overview PDF 331 KB
IDT Clock Generation Overview Overview PDF 1.83 MB


Title language Type Format File Size Date
Timing Commander Personality File for 8V19N850D (v3.2.0) Software & Tools - Other TCP 5.31 MB

memoryBoards & Kits

Part Number Title Type Company
8V19N850-EVK 8V19N850 Evaluation Kit Evaluation Renesas