The 8705I is a highly versatile 1:8 Differential-to- LVCMOS/LVTTL Clock Generator. The 8705I has two selectable clock inputs. The CLK1, nCLK1 pair can accept most standard differential input levels. The single ended CLK0 input accepts LVCMOS or LVTTL input levels.The 8705I has a fully integrated PLL and can be configured as zero delay buffer, multiplier or divider and has an input and output frequency range of 15.625MHz to 250MHz. The reference divider, feedback divider and output divider are each programmable, thereby allowing for the following output- to-input frequency ratios: 8:1, 4:1, 2:1, 1:1, 1:2, 1:4, 1:8. The external feedback allows the device to achieve "zero delay" between the input clock and the output clocks. The PLL_SEL pin can be used to bypass the PLL for system test and debug purposes. In bypass mode, the reference clock is routed around the PLL and into the internal output dividers.

特長

  • Eight LVCMOS/LVTTL outputs, 7Ω typical output impedance
  • Selectable CLK1, nCLK1 or LVCMOS/LVTTL clock inputs
  • CLK1, nCLK1 pair can accept the following differential input levels: LVPECL, LVDS, LVHSTL, HCSL, SSTL
  • CLK0 input accepts LVCMOS or LVTTL input levels
  • Output frequency range: 15.625MHz to 250MHz
  • Input frequency range: 15.625MHz to 250MHz
  • VCO range: 250MHz to 500MHz
  • External feedback for "zero delay" clock regeneration with configurable frequencies
  • Programmable dividers allow for the following output-to-input frequency ratios: 8:1, 4:1, 2:1, 1:1, 1:2, 1:4, 1:8
  • Fully integrated PLL
  • Cycle-to-cycle jitter: 45ps (maximum)
  • Output skew: CLK0, 65ps (maximum) CLK1, nCLK1, 55ps (maximum)
  • Static Phase Offset: 25 ±125ps (maximum), CLK0
  • Full 3.3V or 2.5V operating supply
  • Lead-Free package available
  • -40°C to 85°C ambient operating temperature

tune製品選択

製品名 Part Status Pkg. Type Lead Count (#) Temp. Grade Pb (Lead) Free Carrier Type 購入/サンプル
Obsolete TQFP 32 I はい Tray
Availability
Obsolete TQFP 32 I はい Reel
Availability

descriptionドキュメント

タイトル language 分類 形式 サイズ 日付
データシート
star 8705I Datasheet データシート PDF 371 KB
アプリケーションノート、ホワイトペーパー
AN-828 Termination - LVPECL アプリケーションノート PDF 322 KB
AN-844 Termination - AC Coupling Clock Receivers アプリケーションノート PDF 170 KB
AN-845 Termination - LVCMOS アプリケーションノート PDF 146 KB
AN-842 Thermal Considerations in Package Design and Selection アプリケーションノート PDF 495 KB
AN-840 Jitter Specifications for Timing Signals アプリケーションノート PDF 442 KB
AN-833 Differential Input Self Oscillation Prevention アプリケーションノート PDF 180 KB
AN-834 Hot-Swap Recommendations アプリケーションノート PDF 153 KB
AN-835 Differential Input with VCMR being VIH Referenced アプリケーションノート PDF 160 KB
AN-836 Differential Input to Accept Single-ended Levels アプリケーションノート PDF 120 KB
AN-815 Understanding Jitter Units アプリケーションノート PDF 565 KB
AN-827 Application Relevance of Clock Jitter アプリケーションノート PDF 1.15 MB
AN-805 Recommended Ferrite Beads アプリケーションノート PDF 121 KB
PCN / PDN
PDN# : CQ-18-03 Product Discontinuance Notice 製品中止通知 PDF 218 KB
PCN# : A1602-01(R1) Add Greatek Taiwan as Alternate Assembly 製品変更通知 PDF 611 KB
PCN# : A1602-01 Add Greatek Taiwan as Alternate Assembly 製品変更通知 PDF 611 KB
PCN# : TB1504-01R1 Qty per Reel Standardization for Selective Packages 製品変更通知 PDF 95 KB
PCN# : TB1504-01 Qty per Reel Standardization for Selective Packages 製品変更通知 PDF 50 KB
PCN# : A1401-02 Alternate Copper Wire Assembly Site 製品変更通知 PDF 36 KB
PCN# : TB1303-01 Change of Carrier Tape for TQFP-32, TQFP-48 製品変更通知 PDF 472 KB
その他資料
IDT Clock Distribution Overview (Japanese) English 概要 PDF 7.79 MB
IDT Clock Generation Overview (Japanese) English 概要 PDF 2.19 MB

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