Overview

Description

The 72V2103 256K x 9/128K x 18 SuperSync II FIFO memory has flexible x9/x18 Bus-Matching on both read and write ports. The variable clock cycle counting delay associated with the latency period found on previous SuperSync devices has been eliminated. SuperSync II FIFOs are appropriate for network, video, telecommunications, data communications and other applications that need to buffer large amounts of data and match buses of unequal sizes.

Features

  • Functionally compatible with the 72V255/65/75/85 SuperSync FIFOs
  • Up to 166 MHz Operation of the Clocks
  • User selectable Asynchronous read and/or write ports (BGA Only)
  • User selectable input and output port bus-sizing
  • Pin to Pin compatible to the SuperSync II 72V2x3 devices
  • 5V tolerant inputs
  • Auto power down minimizes standby power consumption
  • Master Reset clears entire FIFO
  • Partial Reset clears data, but retains programmable settings
  • Easily expandable in depth and width
  • JTAG port, provided for Boundary Scan function (BGA Only)
  • Independent Read and Write Clocks
  • Available in 80-pin TQFP or 100-pin BGA packages
  • Industrial temperature range (–40C to +85C) is available

Documentation

Title Type Date
PDF388 KB
Datasheet
PDF211 KB
Application Note
PDF645 KB
End Of Life Notice
PDF123 KB
Guide
PDF24 KB
Product Change Notice
PDF252 KB
Product Change Notice
PDF164 KB
Product Change Notice
PDF290 KB
Product Change Notice
PDF80 KB
Product Change Notice
PDF38 KB
Product Change Notice
PDF26 KB
Product Change Notice
PDF197 KB
Product Change Notice
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PDF150 KB
Product Change Notice
PDF65 KB
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PDF48 KB
Product Change Notice
PDF274 KB
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PDF11 KB
Product Change Notice
PDF44 KB
Product Change Notice

Design & Development

Software & Tools

Software Downloads

Title Type Date
PDF645 KB
End Of Life Notice

Models

Models

Title Type Date
Model - BSDL
ZIP37 KB
Model - IBIS
Model - SPICE

Support