Features
- SMBus write lock feature; increases system security
- PCIe Gen 1–7 compliance
- LP-HCSL outputs with 85Ω Zout; eliminate 24 resistors, save 48mm² of area
- 6 OE# pins; hardware control of each output
- Selectable PLL BW; minimizes jitter peaking in cascaded PLL topologies
- Hardware/SMBus control of PLL bandwidth and bypass; change mode without power cycle
- Spread spectrum compatible; tracks spreading input clock for EMI reduction
- 100MHz PLL Mode; UPI support
- 5mm × 5mm 40-VFQFPN package; small board footprint
Description
The 9ZXL0652E is a second-generation, enhanced-performance DB800ZL differential buffer. The part is functionally compatible with the 9ZXL0652A while offering a much-improved phase jitter performance. A fixed external feedback maintains low drift for critical QPI/UPI applications. The 9ZXL0652E has an SMBus Write Lockout pin for increased device and system security.
Parameters
| Attributes | Value |
|---|---|
| Diff. Outputs | 6 |
| Diff. Output Signaling | LP-HCSL |
| Output Freq Range (MHz) | 1 - 400 |
| Diff. Inputs | 1 |
| Diff. Input Signaling | HCSL |
| Accepts Spread Spec Input | Yes |
| Power Consumption Typ (mW) | 257 |
| Supply Voltage (V) | 3.3 - 3.3 |
| Output Type | LP-HCSL |
| Diff. Termination Resistors | 24 |
| Package Area (mm²) | 81 |
| Battery Backup | No |
| Battery Seal | No |
| CPU Supervisory Function POR | No |
| Crystal Frequency Trimming | No |
| Frequency Out Pin | No |
| Inputs (#) | 1 |
| Input Freq (MHz) | 33 - 150 |
| Function | Zero Delay Buffer |
| Input Type | HCSL |
| Output Banks (#) | 1 |
| Core Voltage (V) | 3.3 |
| Output Voltage (V) | 0.7 |
| Product Category | PCI Express Clocks, Processor Clock Buffers, Zero Delay Buffers |
Package Options
| Pkg. Type | Pkg. Dimensions (mm) | Lead Count (#) | Pitch (mm) |
|---|---|---|---|
| VFQFPN | 5.0 x 5.0 x 0.9 | 40 | 0.4 |
Applications
- Servers/High-performance Computing
- nVME Storage
- Networking
- Accelerators
- Industrial Control