The ADC1210S is a single-channel 12-bit Analog-to-Digital Converter optimized for high dynamic performances and low power consumption. Pipelined architecture and output error correction ensure the ADC1210S is accurate enough to guarantee zero missing codes over the entire operating range. Supplied from a single 3 V source, it can handle output logic levels from 1.8 V to 3.3 V in CMOS mode, by a separate digital output supply. It supports the LVDS DDR output standard. An integrated SPI allows the user to easily configure the ADC. The device also includes a SPI programmable full-scale to allow flexible input voltage range from 1 V to 2 V (peak-to-peak). With excellent dynamic performance from the baseband to input frequencies of 170 MHz or more.
ADC1210S105HN - Block Diagram
12-bit pipelined ADC core
Clock input divider by 2 for less jitter contribution
CMOS or LVDS DDR digital outputs
Duty cycle stabilizer
Fast Out of Range (OTR) detection
Flexible input voltage range: 1 V p-p to 2 V p-p
0.25 LSB, DNL ±
Input bandwidth, 600 MHz
Offset binary, 2's complement, gray code
Pin compatible with the ADC1410S series and the ADC1010S series
IDTs ADC1210S105F1 demoboard is suitable for dynamic performance evaluations from low to high IF configuration with LVCMOS output variants. A data-acquisition board can be used during design and prototype to analyze ADC performance
IDTs ADC1210S105F2 demoboard is suitable for dynamic performance evaluations from low to high IF configuration with LVDS DDR output variants. A data-acquisition board can be used during design and prototype to analyze ADC performance.
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