Features
- Dual chip type
- Low on-state resistance
RDS(on) = 56 mΩ MAX. (VGS = 10 V, ID = 2.5 A)
RDS(on) = 72 mΩ MAX. (VGS = 4.5 V, ID = 2.5 A) - Low gate charge
QG = 13.4 nC TYP. (VGS = 10 V) - Small and surface mount package (SOP-8)
Description
The UPA3753GR is Dual N-channel MOS Field Effect Transistors designed for switching application.
Parameters
| Attributes | Value |
|---|---|
| Qualification Level | Industrial |
| Nch/Pch | Nch |
| Channels (#) | 2 |
| Standard Pkg. Type | SOP-8 / SOIC-8 |
| Gate Level | Logic |
| VDSS (Max) (V) | 60 |
| ID (A) | 5 |
| RDS (ON) (Max) @10V (mohm) | 56 |
| RDS (ON) (Max) @4.5V (mohm) | 72 |
| Pch (W) | 0.85 |
| Ciss (Typical) (pF) | 640 |
| Qg typ (nC) | 13.4 |
| Series Name | UPA Series |
Package Options
| Pkg. Type | Pkg. Dimensions (mm) | Lead Count (#) | Pitch (mm) |
|---|---|---|---|
| SOP | 5 x 4 x 1.75 | 8 | 1.27 |
| Part Number | Status | Samples | Stock | Package | Budgetary Price (USD) | Lead Count (#) | Carrier Type | Moisture Sensitivity Level (MSL) | Pkg. Dimensions (mm) | Pb (Lead) Free | Country of Assembly | Country of Wafer Fabrication |
|---|---|---|---|---|---|---|---|---|---|---|---|---|
| UPA3753GR-E1-AX | Active | Available | In Stock | SOP | 1ku | $0.6 | 8# | Embossed Tape | 1 | 5 x 4 x 1.75 | Yes | MALAYSIA | JAPAN |
| UPA3753GR-E2-AX | Active | N/A | Out of Stock | SOP | 8# | Embossed Tape | 1 | 5 x 4 x 1.75 | Yes | |||
| UPA3753GR-E1-AT | Obsolete | N/A | Out of Stock | SOP | 8# | Embossed Tape | 1 | 5 x 4 x 1.8 | Yes | |||
| UPA3753GR-E2-AT | Obsolete | N/A | Out of Stock | SOP | 8# | Embossed Tape | 1 | 5 x 4 x 1.8 | Yes |
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- Application NotePDF 596 KB R07AN0051EJ0100 Rev.1.00 Apr 27, 2026Compares the thermal performance of automotive power MOSFETs in the TOLL (TO-Leadless) package and its derivatives, including the TOLT (TO-Leaded Top-side Cooling) package. The information presented in this document is intended to serve as a comprehensive guideline for designing high-power automotive systems.
- Application NotePDF 936 KB R07AN0050EJ0100 Rev.1.00 Dec 03, 2025Measurement frequency and the influence of parasitic inductance are crucial in capacitance measurements for Power MOSFETs. Split-gate structures, with their low Crss and higher Ciss, face challenges from parasitic inductance, making high-frequency measurements difficult. In contrast, standard-gate trench structures allow relatively accurate results. The influence of parasitic inductance in actual measurements is examined from various perspectives.
- GuidePDF 988 KB R07ZZ0016EJ0100 Rev.1.00 Dec 03, 2025The diagrams in this document show the recommended mounting pad layout dimensions for Renesas Power MOSFETs. In actual PCB design, optimization should consider mounting density, mountability, dimensional tolerances, and other relevant factors.
- Application NoteAI-generated Summary: Absolute maximum ratings define safe operational limits for MOSFETs, including voltage, current, and temperature thresholds to prevent device damage. Electrical characteristics specify parameters like breakdown voltage, threshold voltage, on-resistance, capacitances, and switching times. Allowable channel dissipation decreases as case temperature rises, calculated by a specific formula. The safe operating area (SOA) outlines five limiting conditions: current rating, on-resistance, channel dissipation, secondary breakdown, and voltage rating, ensuring reliable MOSFET operation under various conditions.
- Application NoteAI-generated Summary: The document outlines derating standards for Power MOSFETs and IGBTs, emphasizing temperature, humidity, voltage, current, and power limits to ensure device reliability. It discusses package type selection between hermetic sealed and plastic molded types, highlighting the advantages of surface-mount packages for miniaturization. It also details precautions for physical handling, including proper lead forming, cutting, and mounting techniques to prevent stress and damage during installation.
Recommended Documents (1)
Datasheets (1)
- GuidePDF 988 KB R07ZZ0016EJ0100 Rev.1.00 Dec 03, 2025The diagrams in this document show the recommended mounting pad layout dimensions for Renesas Power MOSFETs. In actual PCB design, optimization should consider mounting density, mountability, dimensional tolerances, and other relevant factors.
Manuals & Guides (1)
- Application NotePDF 596 KB R07AN0051EJ0100 Rev.1.00 Apr 27, 2026Compares the thermal performance of automotive power MOSFETs in the TOLL (TO-Leadless) package and its derivatives, including the TOLT (TO-Leaded Top-side Cooling) package. The information presented in this document is intended to serve as a comprehensive guideline for designing high-power automotive systems.
- Application NotePDF 936 KB R07AN0050EJ0100 Rev.1.00 Dec 03, 2025Measurement frequency and the influence of parasitic inductance are crucial in capacitance measurements for Power MOSFETs. Split-gate structures, with their low Crss and higher Ciss, face challenges from parasitic inductance, making high-frequency measurements difficult. In contrast, standard-gate trench structures allow relatively accurate results. The influence of parasitic inductance in actual measurements is examined from various perspectives.
- Application NoteAI-generated Summary: Absolute maximum ratings define safe operational limits for MOSFETs, including voltage, current, and temperature thresholds to prevent device damage. Electrical characteristics specify parameters like breakdown voltage, threshold voltage, on-resistance, capacitances, and switching times. Allowable channel dissipation decreases as case temperature rises, calculated by a specific formula. The safe operating area (SOA) outlines five limiting conditions: current rating, on-resistance, channel dissipation, secondary breakdown, and voltage rating, ensuring reliable MOSFET operation under various conditions.
- Application NoteAI-generated Summary: The document outlines derating standards for Power MOSFETs and IGBTs, emphasizing temperature, humidity, voltage, current, and power limits to ensure device reliability. It discusses package type selection between hermetic sealed and plastic molded types, highlighting the advantages of surface-mount packages for miniaturization. It also details precautions for physical handling, including proper lead forming, cutting, and mounting techniques to prevent stress and damage during installation.
Application Notes & White Papers (4)
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