Overview
Description
The SH7046 Series single-chip RISC (Reduced Instruction Set Computer) microprocessors integrate a Renesas-original RISC CPU core with peripheral functions required for system configuration. The SH7046 series CPU has a RISC-type instruction set. Most instructions can be executed in one state (one system clock cycle), which greatly improves instruction execution speed. In addition, the 32-bit internal-bus architecture enhances data processing power. With this CPU, it has become possible to assemble low cost, high performance/high-functioning systems, even for applications that were previously impossible with microprocessors, such as real-time control, which demands high speeds. In addition, the SH7046 series includes on-chip peripheral functions necessary for system configuration, such as large-capacity ROM and RAM, timers, a serial communication interface (SCI), an A/D converter, an interrupt controller (INTC), and I/O ports.
Comparison
Applications
Design & Development
Software & Tools
Sample Code
Models
ECAD Models
Schematic symbols, PCB footprints, and 3D CAD models from SamacSys can be found by clicking on the CAD Model links in the Product Options table. If a symbol or model isn't available, it can be requested directly from SamacSys.

Support
Support Communities
Support Communities
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How to initialise stack pointer in sh7046
Hi,I have a situation like ,I need to initialise stack pointer before execution of my program.After boot mode there will be branching to RAM Area 0xFFFFD800 , here i want to initailise stack pointer and run my main program.0xFFFFD8000 /***initialise stack***/ /***jump to main*****/ ...
Jul 9, 2010 -
SH7046 Simulating
I am working in SH7046 ,while simulating using Hitachi Super H Compiler,I got Memory Access error.what is memory access error and how i can solve it.Can any one help on this ,please.............
Jun 7, 2010
FAQs
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SH Family: What is the difference between the DTC and DMAC?
The DMAC(Direct Memory Access Controller) has registers dedicated to each channel to designate a transfer address, mode and so on. Contrary to this, the DTC(Data Transfer Controller) stores data such as a transfer address, mode in the memory, and once transfer is requested, it reads these data and ...
Mar 24, 2009 -
SH Family: Why is it an advantage to have individual vectors for each peripheral ?
Speed of operation. The CPU does not have to consume time by interrogating a status register to determine which interrupt has been generated.
Mar 18, 2009