Features
- CPU: Cortex-A9 core, Max. 400MHz
- Voltage: 3V to 3.6V
- Package: 176-pin LFBGA
- Memory: SRAM 2MB
- PWM:
- Analog function: 12-bit A/D Converter (ch) x 8
- Others: PLL, RTC, Power-On Reset
RZ/A1LC Block Diagram
Description
The RZ/A1LC MPUs are the most cost-effective part in the RZ/A1 family and feature an Arm® Cortex®-A9 core running at 400MHz and 2MB of on-chip SRAM. With 2MB on-chip SRAM and a 400MHz Arm® Cortex®-A9 core, the RZ/A1LC is a great replacement for MCU designs that are trying to achieve MPU levels of performance. RZ/A1LC enables very compact embedded designs without the need to worry about memory procurement and memory EOL. Enabled for support with Linux, RTOS or Bare-metal, this is the ideal device for designing Intelligent IoT End Point devices with compactness and high performance. Supported in a 176 pin BGA package with SDRAM interface to expand up to 128MB of external memory. Get Started Using RZ/A1 MPUs.
Parameters
| Attributes | Value |
|---|---|
| CPU Architecture | Arm |
| Main CPU | Cortex-A9 |
| Program Memory (KB) | 0 |
| RAM (KB) | 2048 |
| Carrier Type | Bulk (Tray) |
| Supply Voltage (V) | 3 - 3.6 |
| I/O Ports | 100 |
| NPU | No |
| DRAM I/F | SDRAM |
| 3D GPU | No |
| Temp. Range (°C) | Ta = -40 to +85 |
| Operating Freq (Max) (MHz) | 400 |
| Ethernet speed | 10M/100M |
| Ethernet (ch) | 1 |
| EtherCat (ch) (#) | 0 |
| USB FS (host ch/device ch) | ( 0 / 0 ) |
| USB HS (host ch/device ch) | ( 2 / 2 ) |
| USB SS (host ch/device ch) | ( 0 / 0 ) |
| PCI Express (generation and ch) | No |
| SCI or UART (ch) | 5 |
| SPI (ch) | 3 |
| I2C (#) | 4 |
| CAN (ch) | 2 |
| CAN-FD (ch) | 0 |
| Wireless | No |
| SDHI (ch) | 2 |
| High Resolution Output Timer | No |
| PWM Output (pin#) | 16 |
| 32-Bit Timer (ch) | 2 |
| 16-Bit Timer (ch) (#) | 5 |
| 8-Bit Timer (ch) | 0 |
| Standby operable timer | No |
| Asynchronous General Purpose Timer / Interval Timer (ch) | 0 |
| 16-Bit A/D Converter (ch) | 0 |
| 14-Bit A/D Converter (ch) | 0 |
| 12-Bit A/D Converter (ch) | 8 |
| 10-Bit A/D Converter (ch) | 0 |
| 24-Bit Sigma-Delta A/D Converter (ch) | 0 |
| 16-Bit D/A Converter (ch) | 0 |
| 12-Bit D/A Converter (ch) | 0 |
| 10-Bit D/A Converter (ch) (#) | 0 |
| 8-Bit D/A Converter (ch) | 0 |
| Capacitive Touch Sensing Unit (ch) | 0 |
| Graphics LCD Controller | Yes |
| MIPI Interfaces (DSI) (ch) | 0 |
| MIPI Interfaces (CSI) (ch) | 0 |
| Image Codec | No |
| Segment LCD Controller | No |
| Security & Encryption | No |
Package Options
| Pkg. Type | Pkg. Dimensions (mm) | Lead Count (#) | Pitch (mm) |
|---|---|---|---|
| LFBGA | 8 x 8 x 1.4 | 176 | 0.5 |
Applications
- Home Appliance
- Healthcare
| Part Number | Status | Samples | Stock | Package | Budgetary Price (USD) | Carrier Type | Family Name | Series Name | Group Name | CPU Architecture | Main CPU | Sub CPU | Floating Point Unit | Bit Length | Program Memory (KB) | Data Flash (KB) | RAM (KB) | ECC SRAM | Lead Count (#) | Pitch (mm) | Pkg. Dimensions (mm) | Number of Supply Voltage(s) (#) | Supply Voltage (V) | I/O Ports | DMAC or DTC | DMA (ch) | Temperature Sensor (ch) (#) | Power-On Reset | Watchdog Timer (ch) | External Memory Bus (bit) | DRAM I/F | NPU | 3D GPU | Accelerator | MOQ | Temp. Range (°C) | External Interrupt Pins (#) | LVD or PVD | Operating Freq (Max) (MHz) | Sub-clock (32.768 kHz) | On-chip Oscillator | Ethernet speed | Ethernet (ch) | EtherCat (ch) (#) | USB Ports (#) | USB FS (host ch/device ch) | USB HS (host ch/device ch) | USB SS (host ch/device ch) | PCI Express (generation and ch) | SCI or UART (ch) | SPI (ch) | QSPI (ch) | OSPI (ch) | I2C (#) | I3C (ch) | CAN (ch) | CAN-FD (ch) | Wireless | IrDA | LIN (#) | SDHI (ch) | High Resolution Output Timer | PWM Output (pin#) | 32-Bit Timer (ch) | 16-Bit Timer (ch) (#) | 8-Bit Timer (ch) | Standby operable timer | Asynchronous General Purpose Timer / Interval Timer (ch) | RTC | 16-Bit A/D Converter (ch) | 14-Bit A/D Converter (ch) | 12-Bit A/D Converter (ch) | 10-Bit A/D Converter (ch) | 24-Bit Sigma-Delta A/D Converter (ch) | 16-Bit D/A Converter (ch) | 12-Bit D/A Converter (ch) | 10-Bit D/A Converter (ch) (#) | 8-Bit D/A Converter (ch) | Analog Comparator (ch) | OPAMP (ch) (#) | PGA (ch) | Capacitive Touch Sensing Unit (ch) | Graphics LCD Controller | MIPI Interfaces (DSI) (ch) | MIPI Interfaces (CSI) (ch) | Camera I/F (Parallel) | Image Codec | 2D Drawing Engine | Segment LCD Controller | SSI (ch) | Security & Encryption | Debug Interface | Moisture Sensitivity Level (MSL) | Country of Assembly | Country of Wafer Fabrication |
|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|
| R7S721034VCBG#AC0 | Active | Available | In Stock | LFBGA | 1ku | $6 | Bulk (Tray) | RZ | RZ/A | A1LC | Arm | Cortex-A9 | No | Double/Single | 32 | 0 | 0 | 2048KB | No | 176# | 0.5mm | 8 x 8 x 1.4 | 2# | 3 - 3.6 | 100 | DMAC | 16 | 0 | Yes | 1 | 32 | SDRAM | No | No | No | 1 | Ta = -40 to +85 | 108# | No | 400MHz | No | No | 10M/100M | 1ch | 0 | 2# | ( 0 / 0 ) | ( 2 / 2 ) | ( 0 / 0 ) | No | 5 | 3 | 1 | 1 | 4# | 0 | 2 | 0 | No | Yes | 0 | 2 | No | 16 | 2 | 5# | 0 | No | 0 | Yes | 0 | 0 | 8 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | Yes | 0 | 0 | No | No | No | No | 4ch | No | JTAG/SWD | 3 | JAPAN | JAPAN |
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- DocumentPDF 276 KB R01TB0145EJ0100 Rev.1.00 May 21, 2026Essential guidance and reference materials for product development are organized by each development phase, supporting efficient planning and execution. The handbook helps teams align processes, deliverables, and milestones throughout development of the RZ/A1L, RZ/A1LU, and RZ/A1LC.
- Technical Update
- DatasheetPDF 3.71 MB R01DS0480EJ0100 Rev.1.00 Dec 25, 2024
- Manual - HardwareThe RZ/A1LU, RZ/A1L, and RZ/A1LC groups are entry- to mid-range MPUs for HMI applications, featuring an Arm® Cortex®-A9 core (400 MHz) and up to 3 MB of on-chip RAM. With functions optimized for HMI control, these devices are well suited to low-cost and compact HMI equipment. The RZ/A1LU, RZ/A1L, and RZ/A1LC groups hardware manual describes the A9 core subsystem, LCD control, JPEG codec, peripheral interfaces, and related features, providing the information required to design HMI systems that effectively utilize the on-chip RAM.
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- Application NoteAI-generated Summary: This document explains how to automate CUnit tests in Renesas e² studio using EGit and Jenkins. It covers creating a Git repository, pushing code changes via EGit, and setting up Jenkins to build and run CUnit tests automatically. The process includes configuring Jenkins to poll the repository, build the project, execute tests, and generate reports. It also details modifying the SampleC Unit project to link the CUnit static library and output test results to a file for automation.
- Model - BSDL
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- Application NoteAI-generated Summary: Guidelines for designing High-Speed USB 2.0 circuit boards focus on ensuring signal integrity and proper impedance control for 480 Mbps communication. Key points include maintaining a differential impedance of 90 Ω ± 15%, limiting wiring length to 300 mm for host controllers and 100 mm for function controllers, and ensuring minimal length difference between D+ and D- lines (2.5 mm or less). The USB transmission lines must be routed on a single layer without vias, separated from noisy signals, and surrounded by a ground guard ring spaced at least three times the D+/D- line spacing. Power supply pins and USB module pin functions are detailed for proper hardware design. The document also covers layout recommendations such as gentle turns in wiring and ground plane requirements.
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- DatasheetPDF 3.71 MB R01DS0480EJ0100 Rev.1.00 Dec 25, 2024
- DocumentPDF 276 KB R01TB0145EJ0100 Rev.1.00 May 21, 2026Essential guidance and reference materials for product development are organized by each development phase, supporting efficient planning and execution. The handbook helps teams align processes, deliverables, and milestones throughout development of the RZ/A1L, RZ/A1LU, and RZ/A1LC.
- Manual - HardwareThe RZ/A1LU, RZ/A1L, and RZ/A1LC groups are entry- to mid-range MPUs for HMI applications, featuring an Arm® Cortex®-A9 core (400 MHz) and up to 3 MB of on-chip RAM. With functions optimized for HMI control, these devices are well suited to low-cost and compact HMI equipment. The RZ/A1LU, RZ/A1L, and RZ/A1LC groups hardware manual describes the A9 core subsystem, LCD control, JPEG codec, peripheral interfaces, and related features, providing the information required to design HMI systems that effectively utilize the on-chip RAM.
Recommended Documents (3)
- DatasheetPDF 3.71 MB R01DS0480EJ0100 Rev.1.00 Dec 25, 2024
Datasheets (1)
- Manual - HardwareThe RZ/A1LU, RZ/A1L, and RZ/A1LC groups are entry- to mid-range MPUs for HMI applications, featuring an Arm® Cortex®-A9 core (400 MHz) and up to 3 MB of on-chip RAM. With functions optimized for HMI control, these devices are well suited to low-cost and compact HMI equipment. The RZ/A1LU, RZ/A1L, and RZ/A1LC groups hardware manual describes the A9 core subsystem, LCD control, JPEG codec, peripheral interfaces, and related features, providing the information required to design HMI systems that effectively utilize the on-chip RAM.
Manuals & Guides (2)
- Application NoteAI-generated Summary: The document explains how to integrate and use IAR Systems compilers within the e² studio development environment for Renesas microcontrollers. It details the installation of IAR Embedded Workbench and IAR Eclipse plugins, project creation, build configuration, and build execution using IAR compilers. The guide focuses on the RA family with the IAR ARM compiler but applies similarly to other Renesas devices. It also recommends using standalone Flexible Software Package configurators for RA and RZ families to enhance development. The environment setup assumes Windows 10 64-bit, e² studio 2024-07, and IAR tools installed.
- Application NoteAI-generated Summary: This guide explains how to create and build CMake projects using e² studio. It covers installing necessary tools such as e² studio, CMake, and GNU Make, creating a new CMake project, and configuring the builder by disabling the default CDT Core Builder and adding CMake and Make commands. The instructions include setting up environment variables and specifying CMake command parameters to generate native build files from platform-independent CMakeLists.txt configurations.
- Application NoteAI-generated Summary: This document explains how to automate CUnit tests in Renesas e² studio using EGit and Jenkins. It covers creating a Git repository, pushing code changes via EGit, and setting up Jenkins to build and run CUnit tests automatically. The process includes configuring Jenkins to poll the repository, build the project, execute tests, and generate reports. It also details modifying the SampleC Unit project to link the CUnit static library and output test results to a file for automation.
- Application NoteAI-generated Summary: This section explains how to install and configure EGit within the e² studio environment. It details selecting Git integration during e² studio installation, updating EGit via the Help menu, and adding the EGit update repository. The guide also covers setting user identification for Git commits by configuring user name and email in the preferences. Finally, it describes opening the EGit perspective to start using Git features within e² studio.
- Application NoteAI-generated Summary: Guidelines for designing High-Speed USB 2.0 circuit boards focus on ensuring signal integrity and proper impedance control for 480 Mbps communication. Key points include maintaining a differential impedance of 90 Ω ± 15%, limiting wiring length to 300 mm for host controllers and 100 mm for function controllers, and ensuring minimal length difference between D+ and D- lines (2.5 mm or less). The USB transmission lines must be routed on a single layer without vias, separated from noisy signals, and surrounded by a ground guard ring spaced at least three times the D+/D- line spacing. Power supply pins and USB module pin functions are detailed for proper hardware design. The document also covers layout recommendations such as gentle turns in wiring and ground plane requirements.View More (7)
Application Notes & White Papers (7)
- Product Change Notice
- Product Change Notice
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Product Notices (PCN, EOL, etc) (3)
- Technical Update
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- DocumentPDF 276 KB R01TB0145EJ0100 Rev.1.00 May 21, 2026Essential guidance and reference materials for product development are organized by each development phase, supporting efficient planning and execution. The handbook helps teams align processes, deliverables, and milestones throughout development of the RZ/A1L, RZ/A1LU, and RZ/A1LC.
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Partner Boards & Kits
Complementary Silicon Devices
DRAM & Flash Memory Solutions
Provides a comprehensive external memory solution for Renesas RZ and R‑Car families, supporting systems that require scalable off‑chip memory. Supported memory types include Serial NAND (Quad/Octal SPI, 512Mb to 8Gb, 1.8V and 3.3V, 100K/60K cycle endurance), ONFI NAND (ONFI 1.0, 1Gb to 8Gb, 1.8V and 3.3V, 100K/60K cycle endurance), DRAM (DDR2/3/4 from 512Mb to 32Gb and LPDDR2/3/4/4x/5/5x from 1Gb to 16Gb), and HyperRAM™ (HyperBus, 64Mb to 512Mb, 1.8V and 1.2V).
Provided By:
Winbond Electronics Corp. Japan