Overview
Description
RL78/G12 microcontrollers balance the industry's lowest level of consumption current (CPU: 63 μA/MHz, standby (STOP): 230 nA) and a high performance of 32.4 DMIPS (24 MHz). They have an on-chip oscillator, data flash, A/D converter, and more. Built-in safety features (function that detects illegal operation of hardware) enable support for the household appliance safety standard (IEC/UL 60730). With a 20 to 30-pin compact package lineup, these microcontrollers are perfect for sub-microcontrollers of small appliances and consumer and industrial equipment.
Features
- CPU: RL78 core, Max. 24MHz
- Voltage: 1.8V to 5.5V
- Package: 24-pin HWQFN, 20 to 30-pin LSSOP
- Memory: SRAM Max. 2KB, Program Flash Max. 16KB
- Timer: 16-bit Timer (ch) x 8, 8-bit Timer (ch) x 4, Watchdog Timer (ch) x 1, 12-bit Interval Timer x 1 ch
- PWM: PWM Output x 7
- Analog function: 10-bit A/D Converter (ch) x 8
- On-chip Oscillator Freq. (MHz): High-Speed: 1, 4, 8, 12, 16, 24MHz
Low-speed: 15kHz - Others: Power-On Reset, Low Voltage Detection
Comparison
Applications
Design & Development
Support
Support Communities
Support Communities
-
RL78/G12 UART recv isr intermittently misses first char in data frame.
Hello Forum, I have a project where I have been sending a 8 char data frame every 100mS at 9600bps. The frame is the same in every transmission. The recv ISR priority is set to the highest level. No other interrupts have the highest priority. What happens is once every ...
Feb 22, 2018 -
RL78/G12 UART recv isr intermittently misses first char in data frame.
Hello Forum, I have a project where I have been sending a 8 char data frame every 100mS at 9600bps. The frame is the same in every transmission. The recv ISR priority is set to the highest level. No other interrupts have the highest priority. What happens is once every ...
Feb 22, 2018 -
RL78/G12 R5F102AA- Serial code generation error
I am using CS+ to generate serial( UART1 i.e P01 and P00) for R5F102AA 30pin IC. CS+ throwing "E0300004:The setting of pin No. 2 was not changed." error. Please help
Jun 10, 2016
FAQs
-
Tell me the points to be aware of when using the RL78 Code Generator with the WDT.
In the RL78 Code Generator, the Watchdog Timer (WDT) is set to 'Enabled' by default, as shown in the diagram below. To avoid unintended resets by the WDT, please either select 'Disabled' for the 'Watchdog Timer Operation Setting' or add a program to clear the Watchdog Timer counter.
Dec 10, 2024 -
Can the RL78/G13 control an SPI using the SAU?
... until the program is finished processing. Thus, a wait is required after selection by the CS signal from the master. This is described in an RL78/G12 application note, so please refer to it. 1.4 Communication Protocol (Hardware Handshake) in the RL78/G12 Serial Array Unit (CSI ...
Mar 23, 2021 -
RL78 Family: Reset signal generated by the power-on reset circuit (POR)
... D1A, RL78/F12, RL78/F13, RL78/F14, RL78/F15, RL78/F23, RL78/F24, RL78/G10, RL78/G11, RL78/G12, RL78/G13, RL78/G13A, RL78/G14, RL78/G15, RL78/G16, RL78/G1A, RL78/G1C, RL78 ...
Apr 28, 2025