Package Information
| CAD Model: | View CAD Model |
| Pkg. Type: | VFQFPN |
| Pkg. Code: | NDG40 |
| Lead Count (#): | 40 |
| Pkg. Dimensions (mm): | 5.0 x 5.0 x 0.9 |
| Pitch (mm): | 0.4 |
Environmental & Export Classifications
| Moisture Sensitivity Level (MSL) | 1 |
| Pb (Lead) Free | Yes |
| ECCN (US) | EAR99 |
| HTS (US) | 8542.39.0090 |
Product Attributes
| Pkg. Type | VFQFPN |
| Lead Count (#) | 40 |
| Carrier Type | Reel |
| Moisture Sensitivity Level (MSL) | 1 |
| Qty. per Reel (#) | 2500 |
| Qty. per Carrier (#) | 0 |
| Pb (Lead) Free | Yes |
| Pb Free Category | e3 Sn |
| Temp. Range (°C) | -40 to 105°C |
| Additive Jitter | 4fs |
| Additive Phase Jitter Typ RMS (fs) | 33 |
| Additive Phase Jitter Typ RMS (ps) | 0.033 |
| Advanced Features | Automatic Clock Parking, Flexible Power Sequencing and more... |
| App Jitter Compliance | PCIe Gen1, PCIe Gen2, PCIe Gen3, PCIe Gen4, PCIe Gen5, PCIe Gen6, PCIe Gen7 |
| Architecture | Common, SRIS, SRNS |
| Core Voltage (V) | 1.8V, 1.8V |
| Diff. Inputs | 1 |
| Diff. Output Signaling | LP-HCSL |
| Diff. Outputs | 8 |
| Family Name | RC191 |
| Function | Fanout Buffer |
| Input Freq (MHz) | 1 - 400 |
| Input Type | LVDS, HCSL |
| Inputs (#) | 1 |
| Length (mm) | 5 |
| Longevity | 2040 Apr |
| MOQ | 2500 |
| Output Banks (#) | 1 |
| Output Freq Range (MHz) | 1 - 400 |
| Output Impedance | 34, 85, 100 |
| Output Skew (ps) | 36 |
| Output Type | LP-HCSL |
| Output Voltage (V) | 0.8 |
| Outputs (#) | 8 |
| Pitch (mm) | 0.4 |
| Pkg. Dimensions (mm) | 5.0 x 5.0 x 0.9 |
| Power Consumption Typ (mW) | 170 |
| Product Category | Clock Buffers & Drivers, PCI Express Clocks |
| Prog. Interface | SMBus |
| Reel Size (in) | 13 |
| Supply Voltage (V) | 1.8 - 1.8 |
| Tape & Reel | Yes |
| Thickness (mm) | 0.9 |
| VOUT Amplitude Control | Yes |
| VOUT Slew-rate Control | Yes |
| Width (mm) | 5 |
Resources for RC19108A
Description
The RC19108 is a 1.8V 8-output PCIe Gen7 buffer that is backward compatible with earlier PCIe generations. The RC19108 provides ultra-low additive jitter and reduced in-to-out delay performance for better design margin and incorporates several features for easier and more robust design.