Features
- Single 4.5V to 5.5V input voltage range
- Output voltage controlled by host PMIC (P91E0A)
- Up to 6A peak output current per device/phase
- 2.0MHz switching frequency, internal PWM generation
- Support automatic phase-shedding, PFM and LDO modes
- Simple 2-wire interface for device configuration, control and status exchange to the host PMIC
- Automatic detection by Host PMIC
- No analog feedback to PMIC required
- Thermal limit warning flag and load current monitor capability optional
- Automatic load-balancing and heat re-distribution among phases optional
- Digital modulation and ML-based error correction
- Industrial temperature range of -40 °C to +85 °C
- 3mm × 4mm 12-DFN (NRG12)
Description
Flexible output current capabilities are key to address modern multi-core SoC solutions with a variety of different skews. The P9148 distributed power units (DPU) operate as additional phases to the P91E0A PMIC to increase the output current of the solution. The device works as a controlled current source fully controlled by the host PMIC. Multiple P9148 devices may be used in parallel to provide additional current to the load. A high-speed proprietary interface between the P91E0A and the P9148A provides control and feedback information. The device seamlessly integrates into the PMIC ecosystem and is flexible and transparent to the user. P9148A has been designed for systems with a single 5V supply available and supports features such as an optional thermal limit warning flag, load current monitor, and automatic load-balancing among phases).
| Part Number | Status | Samples | Stock | Package | Lead Count (#) | Carrier Type | Moisture Sensitivity Level (MSL) | Pb (Lead) Free | Pb Free Category | Temp. Range (°C) |
|---|---|---|---|---|---|---|---|---|---|---|
| P9148ANRGI8 | Obsolete | N/A | Out of Stock | DFN | 12# | Reel | 1 | Yes | e3 Sn | -40 to 85°C |
Filters
Applied Filters
- Product AdvisoryPDF 203 KB Mar 06, 2026
- Product Change NoticePDF 771 KB Jul 22, 2022
- Application NoteAI-generated Summary: Guidelines focus on optimal component selection, placement, and routing for IDTP9145 PMIC and IDTP9147/9148 DPUs to maximize performance. Minimizing parasitic inductance in PVIN power supply traces is critical, recommending parallel input capacitors to reduce ESL and output capacitors with proper voltage ratings to ensure regulator stability. The PVIN capacitor placement near inner-row PVIN pins requires short traces and multiple parallel vias to reduce parasitic effects. The IDTP9145 offers QFN and HLA packages, with HLA supporting 4-layer PCBs and easier via placement. Proper via arrays connect the exposed pad (power ground) to ground planes, ensuring effective current return. PCB layout examples emphasize minimizing ground plane perforation and careful via usage to maintain current flow and thermal performance.
Recommended Documents (1)
Datasheets (1)
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- Application NoteAI-generated Summary: Guidelines focus on optimal component selection, placement, and routing for IDTP9145 PMIC and IDTP9147/9148 DPUs to maximize performance. Minimizing parasitic inductance in PVIN power supply traces is critical, recommending parallel input capacitors to reduce ESL and output capacitors with proper voltage ratings to ensure regulator stability. The PVIN capacitor placement near inner-row PVIN pins requires short traces and multiple parallel vias to reduce parasitic effects. The IDTP9145 offers QFN and HLA packages, with HLA supporting 4-layer PCBs and easier via placement. Proper via arrays connect the exposed pad (power ground) to ground planes, ensuring effective current return. PCB layout examples emphasize minimizing ground plane perforation and careful via usage to maintain current flow and thermal performance.
Application Notes & White Papers (1)
- Product AdvisoryPDF 203 KB Mar 06, 2026
- Product Change NoticePDF 771 KB Jul 22, 2022
Product Notices (PCN, EOL, etc) (2)
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