Features
- 3 Micron Radiation Hardened SOS CMOS
- Total Dose 200K RAD (Si)
- SEP Effective LET No Upsets: >100 MEV-cm2/mg
- Single Event Upset (SEU) Immunity < 2 x 10-9 Errors/ Bit-Day (Typ)
- Dose Rate Survivability: >1 x 1012 RAD (Si)/s
- Dose Rate Upset >1010 RAD (Si)/s 20ns Pulse
- Latch-Up Free Under Any Conditions
- Fanout (Over Temperature Range)
- Standard Outputs: 10 LSTTL Loads
- Military Temperature Range: -55°C to +125°C
- Significant Power Reduction Compared to LSTTL ICs
- DC Operating Voltage Range: 4.5V to 5.5V
- LSTTL Input Compatibility
- VIL = 0.8V Max
- VIH = VCC/2 Min
- Input Current Levels Ii ≤ 5µA at VOL, VOH
Description
Support is limited to customers who have already adopted these products.
The Intersil HCTS85MS is a Radiation Hardened 4-bit high speed magnitude comparator. This device compares two binary, BCD, or other monotonic codes and presents the three possible magnitude results at the outputs (A>B, A<B, and A=B). The 4-bit input words are weighted (A0 to A3 and B0 to B3), where A3 and B3 are the most significant bits. The HCTS85MS is expandable without external gating, both serial and parallel operation. The HCTS85MS utilizes advanced CMOS/SOS technology to achieve high-speed operation. This device is a member of radiation hardened, high-speed, CMOS/SOS Logic Family with TTL input compatibility. The HCTS85MS is supplied in a 16 lead Ceramic flatpack (K suffix) or a SBDIP Package (D suffix).
| Part Number | Status | Samples | Stock | Package | Lead Count (#) | Carrier Type | Moisture Sensitivity Level (MSL) | DLA SMD | Pb (Lead) Free | Pb Free Category | MOQ | Temp. Range (°C) | CAGE code |
|---|---|---|---|---|---|---|---|---|---|---|---|---|---|
| HCTS85DMSR | Obsolete | N/A | Out of Stock | SBDIP | 16# | Tube | Not Applicable | 5962-95768 | Exempt | Gold Plate over compliant Undercoat-e4 | 25 | -55 to +125°C | 34371 |
Filters
Applied Filters
- End Of Life NoticePDF 163 KB PLC11056 Jun 02, 2011
- Product Change NoticePDF 230 KB PCN10123 Dec 06, 2010
- Application NotePDF 224 KB an9654 May 05, 1999AI-generated Summary: The document explains the reliability and failure mechanisms of semiconductor parts, focusing on life testing and wearout. It discusses how switching states cause transient current pulses and hot carrier injection, which only occur briefly during switching. Life testing at elevated temperatures accelerates aging to remove infant mortality failures, improving reliability. The failure rate follows a bathtub curve with infant mortality, useful life, and wearout phases, modeled by lognormal and exponential distributions. The Arrhenius equation relates failure rates at different temperatures. Burn-in and life tests reduce early failures without harming intrinsic reliability.
Recommended Documents (1)
Datasheets (1)
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- Application NotePDF 224 KB an9654 May 05, 1999AI-generated Summary: The document explains the reliability and failure mechanisms of semiconductor parts, focusing on life testing and wearout. It discusses how switching states cause transient current pulses and hot carrier injection, which only occur briefly during switching. Life testing at elevated temperatures accelerates aging to remove infant mortality failures, improving reliability. The failure rate follows a bathtub curve with infant mortality, useful life, and wearout phases, modeled by lognormal and exponential distributions. The Arrhenius equation relates failure rates at different temperatures. Burn-in and life tests reduce early failures without harming intrinsic reliability.
Application Notes & White Papers (1)
- End Of Life NoticePDF 163 KB PLC11056 Jun 02, 2011
- Product Change NoticePDF 230 KB PCN10123 Dec 06, 2010
Product Notices (PCN, EOL, etc) (2)
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