Package Information
| Lead Count (#) | 8 |
| Pkg. Code | MSL |
| Pitch (mm) | 1.27 |
| Pkg. Type | SOICN |
| Pkg. Dimensions (mm) | 4.90 x 3.91 x 0.00 |
Environmental & Export Classifications
| Moisture Sensitivity Level (MSL) | 3 |
| Pb (Lead) Free | Yes |
| ECCN (US) | EAR99 |
| HTS (US) | 8542390001 |
| RoHS (EL7222CSZ-T13) | Download |
Product Attributes
| Lead Count (#) | 8 |
| Carrier Type | Reel |
| Moisture Sensitivity Level (MSL) | 3 |
| Pb (Lead) Free | Yes |
| Pb Free Category | Pb-Free 100% Matte Tin Plate w/Anneal-e3 |
| Temp. Range | -40 to +85°C |
| Country of Assembly | Malaysia |
| Country of Wafer Fabrication | Taiwan |
| Drivers (#) | 2 |
| Fall Time | 0.013 |
| IS (mA) | 5 |
| Input Signal (Max) | 15 |
| Input Signal (Min) | 0 |
| Input Signal Range | 0 to 15 |
| Input Supply (Max) (VP) | 15 - 15 |
| Input Supply Range (V) | 4.5 - 15 |
| Input Voltage (Max) (V) | 15 |
| Length (mm) | 4.9 |
| MOQ | 2500 |
| Operating Freq (Max) (MHz) | 10 |
| Output Signal (Max) (V) | 15 |
| Output Signal (Min) (V) | 0 |
| Output Signal Range | 0 to +15 |
| Parametric Category | Low-Side FET Drivers |
| Peak Output Current IPK (A) | 2 |
| Pitch (mm) | 1.3 |
| Pkg. Dimensions (mm) | 4.9 x 3.9 x 0.00 |
| Pkg. Type | SOICN |
| Qualification Level | Standard |
| RDS (ON) (Ohms) | 4 |
| Rise Time (μs) | 10 |
| Thickness (mm) | 0.00 |
| Turn Off Delay (ns) | 20 |
| Turn On Delay (ns) | 18 |
| VBIAS (Min) (V) | 4.5 |
| Width (mm) | 3.9 |
Description
The EL7202, EL7212, EL7222 ICs are matched dual-drivers that improve the operation of the industry standard DS0026 clock drivers. The Elantec versions are very High-Speed drivers capable of delivering peak currents of 2. 0 amps into highly capacitive loads. The High-Speed performance is achieved by means of a proprietary Turbo-Driver circuit that speeds up input stages by tapping the wider voltage swing at the output. Improved speed and drive capability are enhanced by matched rise and fall delay times. These matched delays maintain the integrity of input-to-output pulse-widths to reduce timing errors and clock skew problems. This improved performance is accompanied by a 10 fold reduction in supply currents over bipolar drivers, yet without the delay time problems commonly associated with CMOS devices. Dynamic switching losses are minimized with non-overlapped drive techniques.