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9ZXL1550D

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15-Output DB1900ZL PCIe Zero-Delay/Fanout Clock Buffer

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Features

  • LP-HCSL outputs with 85Ω Zout; eliminate 60 resistors, save 103mm² of area
  • PCIe Gen 1–5 compliance
  • SMBus OE bits; software control of each output
  • 9 selectable SMBus addresses; multiple devices can share the same SMBus segment
  • Selectable PLL BW; minimizes jitter peaking in cascaded PLL topologies
  • Hardware/SMBus control of PLL bandwidth and bypass; change mode without power cycle
  • Spread spectrum compatible; tracks spreading input clock for EMI reduction
  • 9mm x 9mm 64-VFQFPN package; small board footprint
Find Other Products in Application-Specific Clocks
9ZXL15x0D-19xxD - Block Diagram
9ZXL1550D - Pinout
9ZXL15x0D-19xxD - Block Diagram
9ZXL1550D - Pinout

Description

The 9ZXL1550D is a second-generation enhanced-performance DB1900Z-derivative differential buffer. The part is a pin-compatible upgrade to the 9ZXL1550B while offering a much-improved phase jitter performance. A fixed external feedback maintains low drift for critical QPI/UPI applications.

Parameters

AttributesValue
Diff. Outputs15
Diff. Output SignalingLP-HCSL
Output Freq Range (MHz)1 - 400
Diff. Inputs1
Diff. Input SignalingHCSL
Accepts Spread Spec InputYes
Power Consumption Typ (mW)521
Supply Voltage (V)3.3 - 3.3
Output TypeLP-HCSL
Diff. Termination Resistors30
Package Area (mm²)81
Battery BackupNo
Battery SealNo
CPU Supervisory Function PORNo
Crystal Frequency TrimmingNo
Frequency Out PinNo
Inputs (#)1
Input Freq (MHz)33 - 150
FunctionZero Delay Buffer
Input TypeHCSL
Output Banks (#)1
Core Voltage (V)3.3
Output Voltage (V)0.7

Package Options

Pkg. TypePkg. Dimensions (mm)Lead Count (#)Pitch (mm)
VFQFPN9.0 x 9.0 x 0.9640.5

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Introducing Renesas’ enhanced PCIe clock buffer family. These PCIe Gen5 clock buffers offer fanout and zero-delay operating modes, supporting both legacy systems and the most complex timing trees within a single device. Unlike many existing solutions, whose performance limitations force their use in fanout buffer mode, these clock buffers meet both PCIe Gen5 and prominent CPU-specific phase jitter requirements in all operating modes. The extremely low 50fs rms PCIe Gen5 additive phase jitter enables multi-level cascading within the strict PCIe Gen5 jitter budget. Renesas’ high-performance oscillators and clock generators provide an ideal clock source for the enhanced PCIe clock buffer family. 

For more information about these PCIe Gen5 clock buffers, visit the PCIe timing page.

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