Features
- DIF output cycle-to-cycle jitter < 50ps
- DIF output-to-output skew < 150 ps
- PCIe Gen2 compliant phase noise
- QPI 133MHz compliant phase noise
- Supports output clock frequencies up to 400 MHz
- 4 Selectable SMBus addresses
- SMBus address is independent of PLL operating mode
- Dedicated CKPWRGD/PD# and VDDA pins ease board design
- Available in industrial temperature range (-40°C to +85°C)
9EX21801A - Block Diagram
Description
The 9EX21801 provides 18 output clocks for PCIe Gen2 (100MHz) or QPI (133MHz) applications. The 9EX21801 has 4 selectable SMBus addresses, and dedicated CKPWRGD/PD# and VDDA pins for easy board design. A differential CPU clock from a CK410B+ main clock generator, such as the 932S421, drives the 9EX21801. In fanout mode, the 9EX21801 provides outputs up to 400MHz.
| Part Number | Status | Samples | Stock | Package | Lead Count (#) | Carrier Type | Moisture Sensitivity Level (MSL) | Input Freq (MHz) | Output Freq Range (MHz) | Qty. per Reel (#) | Qty. per Carrier (#) | Pb (Lead) Free | Pb Free Category | Temp. Range (°C) |
|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|
| 9EX21801AKILF | Obsolete | N/A | Out of Stock | VFQFPN | 72# | Tray | 3 | 80 - 150 | 80 - 150 | 0 | 168# | Yes | e3 Sn | -40 to 85°C |
| 9EX21801AKILFT | Obsolete | N/A | Out of Stock | VFQFPN | 72# | Reel | 3 | 80 - 150 | 80 - 150 | 2500# | 0 | Yes | e3 Sn | -40 to 85°C |
| 9EX21801AKLF | Obsolete | N/A | Out of Stock | VFQFPN | 72# | Tray | 3 | 166 | 33.33 - 400 | 0 | 168# | Yes | e3 Sn | 0 to 70°C |
| 9EX21801AKLFT | Obsolete | N/A | Out of Stock | VFQFPN | 72# | Reel | 3 | 166 | 33.33 - 400 | 2500# | 0 | Yes | e3 Sn | 0 to 70°C |
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- Application NotePDF 170 KB 7WDXRDKU4E7E-5-57318 May 13, 2014
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- Product Change NoticePDF 103 KB 7WDXRDKU4E7E-5-55965 Aug 18, 2013
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- End Of Life NoticePDF 606 KB 7WDXRDKU4E7E-5-62524 Nov 29, 2017
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- Application NotePDF 1.99 MB 7WDXRDKU4E7E-5-57242 Mar 01, 2022
- Application NotePDF 170 KB 7WDXRDKU4E7E-5-57318 May 13, 2014
- Application NotePDF 1.9 MB 7WDXRDKU4E7E-5-57315 May 13, 2014View More (10)
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- End Of Life NoticePDF 606 KB 7WDXRDKU4E7E-5-62524 Nov 29, 2017
- End Of Life NoticePDF 599 KB 7WDXRDKU4E7E-5-61808 Aug 24, 2017
- Product Change NoticePDF 583 KB 7WDXRDKU4E7E-5-61343 Dec 20, 2016
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This is the first video in our PCIe series. In this video, we define PCIe architectures, focusing on common and separate clock architectures. Watch the rest of the video series below where Ron will cover the impact of different timing architectures.
In this episode, Ron Wade from IDT (acquired by Renesas) explains PCIe common clocking and its impact on timing solutions. Learn about using a single clock source, fan-out buffers, and the considerations for spread spectrum and non-spread spectrum clocking in PCIe systems.
In this video, we explore PCIe with separate reference clocks and the effects of clock selection. Learn how separate reference clocks work and their impact on system performance and stability.
This video provides a high-level overview of Separate Reference Clock with Independent Spread (SRIS) architectures for PCI Express systems, additional performance requirements that this clocking architecture imposes on the reference clocks, and some system implications encountered trying to implement the architecture.
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