Overview
Description
The 8V31012 is a 1-to-12 differential HCSL fanout buffer designed to translate any differential signal levels to differential HCSL output levels. An external reference resistor is used to set the value of the current supplied to an external load/termination resistor. The load resistor value is chosen to equal the value of the characteristic line impedance of 50Ω. The 8V31012 is characterized to an operating supply voltage of 3.3V.
The differential HCSL outputs, accurate crossover voltage, and duty cycle make the 8V31012 ideal for interfacing to PCI Express and FBDIMM applications.
Features
- Twelve differential HCSL outputs
- Translates any differential input signal (LVPECL, LVHSTL, LVDS, HCSL) to HCSL levels without external bias networks
- Maximum output frequency: 250MHz
- Output skew: 265ps (typical)
- VOH: 850mV (maximum)
- Full 3.3V supply voltage
- Available in a lead-free (RoHS 6) package
- -40 °C to 85 °C ambient operating temperature
Comparison
Applications
Design & Development
Models
ECAD Models
Schematic symbols, PCB footprints, and 3D CAD models from SamacSys can be found by clicking on the CAD Model links in the Product Options table. If a symbol or model isn't available, it can be requested directly from SamacSys.
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Videos & Training
PCIe Clocking Architectures (Common and Separate)
This is the first video in our PCIe series. In this video, we define PCIe architectures, focusing on common and separate clock architectures. Watch the rest of the video series below where Ron will cover the impact of different timing architectures.
Watch the Video Series Below
Video List
