Renesas’ Timing product portfolio has been acquired by SiTime.
Datasheets, documentation, and sample orders remain available on Renesas.com through late 2026. For new designs, purchasing, support, and product inquiries, visit SiTime.com or send an email to [email protected]. Full transition to SiTime is expected by late 2026.
| CAD Model: | View CAD Model |
| Pkg. Type: | VFQFPN |
| Pkg. Code: | NLG72 |
| Lead Count (#): | 72 |
| Pkg. Dimensions (mm): | 10.0 x 10.0 x 1.0 |
| Pitch (mm): | 0.5 |
| Moisture Sensitivity Level (MSL) | 3 |
| Pb (Lead) Free | Yes |
| ECCN (US) | EAR99 |
| HTS (US) | 8542.39.0090 |
| Lead Count (#) | 72 |
| Carrier Type | Reel |
| Moisture Sensitivity Level (MSL) | 3 |
| Qty. per Reel (#) | 2500 |
| Qty. per Carrier (#) | 0 |
| Pb (Lead) Free | Yes |
| Pb Free Category | e3 Sn |
| Temp. Range (°C) | -40 to 85°C |
| Country of Assembly | TAIWAN |
| Country of Wafer Fabrication | TAIWAN |
| Accepts Spread Spec Input | Yes |
| Additive Phase Jitter Typ RMS (fs) | 109 |
| Advanced Features | Multiple SMBus addresses, HW PLL mode control, SW PLL mode control, Programmable input-to-output skew |
| App Jitter Compliance | PCIe Gen1, PCIe Gen2, PCIe Gen3, PCIe Gen4, QPI, UPI, 25G EDR, IF-UPI |
| Architecture | Common, SRIS, SRNS |
| C-C Jitter Max P-P (ps) | 50 |
| Chipset Manufacturer | Intel |
| Chipset Name | C600, Patsburg, Wellsburg, Lewisburg |
| Clock Spec. | DB1200ZL v0.8 Derivative Mux |
| Core Voltage (V) | 3.3V |
| Diff. Input Signaling | HCSL |
| Diff. Inputs | 2 |
| Diff. Output Signaling | LP-HCSL |
| Diff. Outputs | 12 |
| Diff. Termination Resistors | 24 |
| Feedback Input | No |
| Function | Multiplexer |
| Input Freq (MHz) | 33 - 150 |
| Input Type | HCSL |
| Inputs (#) | 2 |
| Length (mm) | 10 |
| MOQ | 2500 |
| Output Banks (#) | 1 |
| Output Enable (OE) Pins | 12 |
| Output Freq Range (MHz) | 1 - 400 |
| Output Impedance | 85 |
| Output Skew (ps) | 50 |
| Output Type | LP-HCSL |
| Output Voltage (V) | 0.7V |
| Outputs (#) | 12 |
| PLL | Yes |
| Package Area (mm²) | 100 |
| Pitch (mm) | 0.5 |
| Pkg. Dimensions (mm) | 10.0 x 10.0 x 1.0 |
| Pkg. Type | VFQFPN |
| Power Consumption Typ (mW) | 482 |
| Product Category | Clock Multiplexers, PCI Express Clocks, Processor Clock Buffers, Zero Delay Buffers |
| Prog. Clock | Yes |
| Prog. Interface | SMBUS |
| Reel Size (in) | 13 |
| Reference Output | No |
| Spread Spectrum | Yes |
| Supply Voltage (V) | 3.3 - 3.3 |
| Tape & Reel | Yes |
| Thickness (mm) | 1 |
| Width (mm) | 10 |
The 9ZML1252E is a second-generation 2-input/12-output differential mux for Intel Purley and newer platforms. It exceeds the demanding DB1200ZL performance specifications and is backward compatible with the 9ZML1232B. The device utilizes Low Power HCSL-compatible outputs to reduce power consumption and termination resistors. It is suitable for PCI Express Gen 1-4 or QPI/UPI applications, and provides two configurable low-drift I2O settings, one for each input channel, to allow I2O tuning for various topologies.