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DDR I/DDR II Phase Lock Loop Zero Delay Buffer

Package Information

Lead Count (#) 28
Pkg. Dimensions (mm) 9.7 x 4.4 x 1.0
Pkg. Code PGG28
Pitch (mm) 0.65
Pkg. Type TSSOP

Environmental & Export Classifications

Moisture Sensitivity Level (MSL) 1
Pb (Lead) Free Yes
ECCN (US) NLR
HTS (US) 8542390001

Product Attributes

Lead Count (#) 28
Carrier Type Reel
Moisture Sensitivity Level (MSL) 1
Qty. per Reel (#) 2000
Qty. per Carrier (#) 0
Package Area (mm²) 42.7
Pkg. Dimensions (mm) 9.7 x 4.4 x 1.0
Pb (Lead) Free Yes
Pb Free Category e3 Sn
Temp. Range 0 to 70°C
Accepts Spread Spec Input Yes
Advanced Features Accepts Spread Spec Input, Reference Output
App Jitter Compliance DDR, DDR2
C-C Jitter Max P-P (ps) 50
Core Voltage (V) 1.8, 2.5
Delay Mode Variable
Die Form No
Diff. Input Signaling SSTL-2
Diff. Output Signaling SSTL-2
Input Freq (MHz) 125 - 0
Input Type LVCMOS
Inputs (#) 4
Length (mm) 9.7
MOQ 2000
Output Banks (#) 1
Output Freq Range (MHz) 125 - 0
Output Skew (ps) 40
Output Type SSTL-2
Output Voltage (V) 2.5, 1.8
Outputs (#) 6
Period Jitter Max P-P (ps) 30.000
Pitch (mm) 0.65
Pkg. Type TSSOP
Reel Size (in) 13
Reference Output Yes
Requires Terms and Conditions Does not require acceptance of Terms and Conditions
Spread Spectrum No
Tape & Reel Yes
Thickness (mm) 1
Width (mm) 4.4

Description

DDR I/DDR II Phase Lock Loop Zero Delay Buffer