Overview
Description
The 9FGV1008 is a member of Renesas' PhiClock™ programmable clock generator family. The 9FGV1008 provides one integer frequency, one copy of a fractional or spread spectrum output frequency, and one copy of the crystal reference input. Two select pins allow for hardware selection of the desired configuration, or two I2C bits allow easy software selection of the desired configuration. The user may configure any one of the four OTP configurations as the default when operating in I2C mode. Four unique I2C addresses are available, allowing easy I2C access to multiple components.
Features
- PCIe Gen1–4 compliant
- 224fs RMS typical phase jitter at 156.25MHz (12kHz–20MHz)
- 2 programmable output pairs plus 1 LVCMOS REF output
- 1 integer and 1 fractional or spread-spectrum output per configuration
- 1MHz–325MHz integer outputs (LVDS or LP-HCSL)
- 1MHz–200MHz integer outputs (LVCMOS)
- 1.8V to 3.3V core VDD
- Individual 1.8V to 3.3V VDDO for each programmable output pair
- Supports HCSL, LVDS and LVCMOS I/O standards
- Supports AC-coupled LVPECL and CML logic – see AN-891
- 3 × 3 mm 16-LGA packages with 50MHz integrated crystal option
- Supported by Timing Commander™ software
Comparison
Applications
Design & Development
Software & Tools
Boards & Kits
Evaluation
EVK9FGV1008
Preview
Evaluation Kit for 9FGV1008 Programmable PhiClock™ Generator
This is the evaluation board for the 9FGV1008 programmable PhiClockTM generator. It provides a convenient way of configuring and programming the blank parts for the 9FGV1008 device. With the onboard USB interface, the Renesas Timing CommanderTM graphical user interface (GUI) can communicate with...
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Models
ECAD Models
Schematic symbols, PCB footprints, and 3D CAD models from SamacSys can be found by clicking on the CAD Model links in the Product Options table. If a symbol or model isn't available, it can be requested directly from SamacSys.
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Videos & Training
PCIe Reference Clock Jitter Budgets
Ron Wade, chief PCIe system architect explains the fundamental difference in reference clock jitter budgets between the first three generations of the specification and those of Gen4 and Gen5 which raise new challenges for designers.
Related Resources
Video List
News & Blog Posts
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Apr 30, 2018
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