Features
- LP-HCSL outputs; save 12 resistors compared to standard PCIe devices
- 45 mW typical power consumption; reduced thermal concerns
- Outputs can optionally be supplied from any voltage between 1.05 and 1.5 V; maximum power savings
- OE# pins; support DIF power management
- Programmable slew rate for each output; allows tuning for various line lengths
- Programmable output amplitude; allows tuning for various application environments
- DIF outputs blocked until PLL is locked; clean system start-up
- Selectable 0%, -0.25% or -0.5% spread on DIF outputs; reduces EMI
- External 25 MHz crystal; supports tight ppm with 0 ppm synthesis error
- Configuration can be accomplished with strapping pins; SMBus interface not required for device control
- 3.3 V tolerant SMBus interface works with legacy controllers
- Space saving 5x5mm 40-pin VFQFPN; minimal board space
- Selectable SMBus addresses; multiple devices can easily share an SMBus segment
Description
The 9FGU0631 is a member of IDT's 1.5 V Ultra-Low-Power PCIe clock family. The device has 6 output enables for clock management, 2 different spread spectrum levels in addition to spread off, and 2 selectable SMBus addresses.
| Part Number | Status | Samples | Stock | Package | Lead Count (#) | Carrier Type | Moisture Sensitivity Level (MSL) | Qty. per Reel (#) | Qty. per Carrier (#) | Pb (Lead) Free | Pb Free Category | Temp. Range (°C) |
|---|---|---|---|---|---|---|---|---|---|---|---|---|
| 9FGU0631CKILF | Obsolete | N/A | Out of Stock | VFQFPN | 40# | Tray | 3 | 0 | 490# | Yes | e3 Sn | -40 to 85°C |
| 9FGU0631CKILFT | Obsolete | N/A | Out of Stock | VFQFPN | 40# | Reel | 3 | 2500# | 0 | Yes | e3 Sn | -40 to 85°C |
| 9FGU0631CKLF | Obsolete | N/A | Out of Stock | VFQFPN | 40# | Tray | 3 | 0 | 490# | Yes | e3 Sn | 0 to 70°C |
| 9FGU0631CKLFT | Obsolete | N/A | Out of Stock | VFQFPN | 40# | Reel | 3 | 2500# | 0 | Yes | e3 Sn | 0 to 70°C |
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- Application NotePDF 431 KB 7WDXRDKU4E7E-5-59216 Dec 06, 2023
- End Of Life NoticePDF 1.22 MB Sep 07, 2022
- End Of Life NoticePDF 1.15 MB Aug 15, 2022
- Product Change NoticePDF 728 KB May 13, 2022
- Application NotePDF 307 KB 7WDXRDKU4E7E-5-59989 Mar 10, 2016
- Application NotePDF 235 KB 7WDXRDKU4E7E-5-58851 Apr 08, 2015
- Application NotePDF 1.9 MB 7WDXRDKU4E7E-5-57315 May 13, 2014
- Application NotePDF 495 KB 7WDXRDKU4E7E-5-57312 May 12, 2014
- Application NotePDF 442 KB 7WDXRDKU4E7E-5-57298 May 08, 2014
- Application NotePDF 136 KB 7WDXRDKU4E7E-5-57044 Mar 12, 2014
- Product Change NoticePDF 361 KB 7WDXRDKU4E7E-5-55130 Mar 24, 2013
Recommended Documents (1)
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- Application NotePDF 431 KB 7WDXRDKU4E7E-5-59216 Dec 06, 2023
- Application NotePDF 1.99 MB 7WDXRDKU4E7E-5-57242 Mar 01, 2022
- Application NotePDF 307 KB 7WDXRDKU4E7E-5-59989 Mar 10, 2016
- Application NotePDF 235 KB 7WDXRDKU4E7E-5-58851 Apr 08, 2015View More (11)
Application Notes & White Papers (11)
- End Of Life NoticePDF 1.22 MB Sep 07, 2022
- End Of Life NoticePDF 1.15 MB Aug 15, 2022
- Product Change NoticePDF 728 KB May 13, 2022
- Product Change NoticePDF 983 KB Jun 25, 2019
- Product Change NoticePDF 361 KB 7WDXRDKU4E7E-5-55130 Mar 24, 2013
Product Notices (PCN, EOL, etc) (5)
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This is the first video in our PCIe series. In this video, we define PCIe architectures, focusing on common and separate clock architectures. Watch the rest of the video series below where Ron will cover the impact of different timing architectures.
In this episode, Ron Wade from IDT (acquired by Renesas) explains PCIe common clocking and its impact on timing solutions. Learn about using a single clock source, fan-out buffers, and the considerations for spread spectrum and non-spread spectrum clocking in PCIe systems.
In this video, we explore PCIe with separate reference clocks and the effects of clock selection. Learn how separate reference clocks work and their impact on system performance and stability.
This video provides a high-level overview of Separate Reference Clock with Independent Spread (SRIS) architectures for PCI Express systems, additional performance requirements that this clocking architecture imposes on the reference clocks, and some system implications encountered trying to implement the architecture.
IDT (acquired by Renesas) engineer provides a brief tutorial describing the main differences between standard HCSL and low-power HCSL (LP-HCSL).
Presented by Ron Wade, PCI Express timing expert.
An overview of IDT's full-featured PCI Express (PCIe) clock generators addressing PCIe Gen 1, Gen 2, Gen 3, and Gen 4.
Presented by Ron Wade, System Architect at IDT.
An overview of PCI Express applications and how IDT's industry-leading portfolio of PCIe clock products addresses the requirements. The video briefly discusses PCIe riser cards, embedded SOC, and PCIe storage (NVME) examples.
Presented by Ron Wade, System Architect at IDT.
A brief overview of how data rates have changed from PCI Express (PCIe) Generation 1, Gen 2, Gen 3, Gen 4 and Gen 5.
Presented by Ron Wade, system architect at IDT.
A brief overview of how clock and timing specifications have changed from PCI Express (PCIe) Generation 1, Gen 2, Gen 3, Gen 4 and Gen 5.
Presented by Ron Wade, system architect at IDT (acquired by Renesas).
A brief overview of the PCI Express common clock (CC) jitter model, and the transfer functions as they relate to the timing PLLs. This model applies to PCI Express (PCIe) Gen 2, Gen 3, Gen 4 and Gen 5. The equations would be slightly different for other PCIe architectures, such as SRIS, SRnS, or data clocked.
Presented by Ron Wade, system architect at IDT (acquired by Renesas). For more information about Renesas's PCIe timing solutions, visit the PCI Express (PCIe) Clocks page.
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