Features
- 4 - 0.7 V current mode differential HCSL output pairs
- 1 - 3.3 V LVTTL REF output
- Pin-to-Pin with 9FG104D/Easy upgrade to PCIe Gen3
- Generates common frequencies from 14.318 MHz or 25 MHz; single part supports multiple applications
- Provides copy of reference output; eliminates need for additional crystal or oscillator
- Unused outputs may be disabled in Hi-Z save system power
- Device may be configured by SMBus and/or strap pins; can be used in systems without SMBus
- Cycle-to-cycle jitter: < 50 ps with 25 MHz input
- Output-to-output skew: <50 ps
- Phase jitter: PCIe Gen3 < 1 ps RMS
- Phase jitter: QPI 9.6 GB/s < 0.2 ps RMS
- 10 ppm synthesis error with 25 MHz input and Spread Off
9FG430 - Block Diagram
Description
The 9FG430 is a Frequency Timing Generator that provides 4 HCSL differential output pairs. These outputs support PCI-Express Gen3, and QPI applications. The part supports Spread Spectrum and synthesizes several additional output frequencies from either a 14.31818 MHz crystal, a 25 MHz crystal or reference input clock. The 9FG430 also outputs a copy of the reference clock. Complete control of the device is available via strapping pins or via the SMBus interface.
| Part Number | Status | Samples | Stock | Package | Lead Count (#) | Carrier Type | Moisture Sensitivity Level (MSL) | Qty. per Reel (#) | Qty. per Carrier (#) | Package Area (mm²) | Pkg. Dimensions (mm) | Pb (Lead) Free | Pb Free Category | Temp. Range (°C) |
|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|
| 9FG430AFILF | Obsolete | N/A | Out of Stock | SSOP | 28# | Tube | 1 | 0 | 47# | 54.1mm² | 10.2 x 5.3 x 1.73 | Yes | e3 Sn | -40 to 85°C |
| 9FG430AFILFT | Obsolete | N/A | Out of Stock | SSOP | 28# | Reel | 1 | 1500# | 0 | 54.1mm² | 10.2 x 5.3 x 1.73 | Yes | e3 Sn | -40 to 85°C |
| 9FG430AFLF | Obsolete | N/A | Out of Stock | SSOP | 28# | Tube | 1 | 0 | 47# | 54.1mm² | 10.2 x 5.3 x 1.73 | Yes | e3 Sn | 0 to 70°C |
| 9FG430AFLFT | Obsolete | N/A | Out of Stock | SSOP | 28# | Reel | 1 | 1500# | 0 | 54.1mm² | 10.2 x 5.3 x 1.73 | Yes | e3 Sn | 0 to 70°C |
| 9FG430AGILF | Obsolete | N/A | Out of Stock | TSSOP | 28# | Tube | 1 | 0 | 50# | 42.7mm² | 9.7 x 4.4 x 1.0 | Yes | e3 Sn | -40 to 85°C |
| 9FG430AGILFT | Obsolete | N/A | Out of Stock | TSSOP | 28# | Reel | 1 | 2000# | 0 | 42.7mm² | 9.7 x 4.4 x 1.0 | Yes | e3 Sn | -40 to 85°C |
| 9FG430AGLF | Obsolete | N/A | Out of Stock | TSSOP | 28# | Tube | 1 | 0 | 50# | 42.7mm² | 9.7 x 4.4 x 1.0 | Yes | e3 Sn | 0 to 70°C |
| 9FG430AGLFT | Obsolete | N/A | Out of Stock | TSSOP | 28# | Reel | 1 | 2000# | 0 | 42.7mm² | 9.7 x 4.4 x 1.0 | Yes | e3 Sn | 0 to 70°C |
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- Application NotePDF 187 KB R31AN0065EU0101 Rev.1.01 Nov 14, 2023
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- Application NotePDF 187 KB R31AN0065EU0101 Rev.1.01 Nov 14, 2023
- Application NotePDF 1.99 MB 7WDXRDKU4E7E-5-57242 Mar 01, 2022
- Application NotePDF 307 KB 7WDXRDKU4E7E-5-59989 Mar 10, 2016View More (16)
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- End Of Life NoticePDF 859 KB Mar 24, 2022
- End Of Life NoticePDF 606 KB 7WDXRDKU4E7E-5-62524 Nov 29, 2017
- End Of Life NoticePDF 599 KB 7WDXRDKU4E7E-5-61808 Aug 24, 2017
- Product Change NoticePDF 611 KB 7WDXRDKU4E7E-5-60321 Apr 14, 2016
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This is the first video in our PCIe series. In this video, we define PCIe architectures, focusing on common and separate clock architectures. Watch the rest of the video series below where Ron will cover the impact of different timing architectures.
In this episode, Ron Wade from IDT (acquired by Renesas) explains PCIe common clocking and its impact on timing solutions. Learn about using a single clock source, fan-out buffers, and the considerations for spread spectrum and non-spread spectrum clocking in PCIe systems.
In this video, we explore PCIe with separate reference clocks and the effects of clock selection. Learn how separate reference clocks work and their impact on system performance and stability.
This video provides a high-level overview of Separate Reference Clock with Independent Spread (SRIS) architectures for PCI Express systems, additional performance requirements that this clocking architecture imposes on the reference clocks, and some system implications encountered trying to implement the architecture.
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