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Renesas’ Timing product portfolio has been acquired by SiTime.

Datasheets, documentation, and sample orders remain available on Renesas.com through late 2026. For new designs, purchasing, support, and product inquiries, visit SiTime.com or send an email to [email protected]. Full transition to SiTime is expected by late 2026.

9DBL06 Block Diagram
9DBL06 Pinout
3D illustration featuring top and bottom views of VFQFPN IC chip package with 40 lead count.
9DBL06 Block Diagram
9DBL06 Pinout
3D illustration featuring top and bottom views of VFQFPN IC chip package with 40 lead count.

9DBL0651BKILF

Obsolete
6-Output 3.3V PCIe Zero-Delay/Fanout Clock Buffer
9DBL02x2/9DBL04x2/9DBL06x1/9DBL08x1C Datasheet9DBL02x2-04x2-06x1-08x1 Family DatasheetLearn more about 9DBL0651

Package Information

CAD Model:View CAD Model
Pkg. Type:VFQFPN
Pkg. Code:NDG40
Lead Count (#):40
Pkg. Dimensions (mm):5.0 x 5.0 x 0.9
Pitch (mm):0.4

Environmental & Export Classifications

Moisture Sensitivity Level (MSL)3
Pb (Lead) FreeYes
ECCN (US)EAR99
HTS (US)8542.39.0090

Product Attributes

Lead Count (#)40
Carrier TypeTray
Moisture Sensitivity Level (MSL)3
App Jitter CompliancePCIe Gen1, PCIe Gen2, PCIe Gen3, PCIe Gen4, PCIe Gen5
Qty. per Reel (#)0
Qty. per Carrier (#)490
Pb (Lead) FreeYes
Pb Free Categorye3 Sn
Temp. Range (°C)-40 to 85°C
Accepts Spread Spec InputYes
Additive Phase Jitter Typ RMS (fs)300
Additive Phase Jitter Typ RMS (ps)0.3
Advanced FeaturesMultiple SMBus addresses
ArchitectureCommon, SRNS, SRIS
C-C Jitter Max P-P (ps)50
Core Voltage (V)3.3V
Diff. Input SignalingHCSL
Diff. Inputs1
Diff. Output SignalingLP-HCSL
Diff. Outputs6
Diff. Termination Resistors0
Feedback InputNo
FunctionZero Delay Buffer
Input Freq (MHz)1 - 200
Input TypeHCSL
Inputs (#)1
Length (mm)5
MOQ490
Output Banks (#)1
Output Freq Range (MHz)1 - 200
Output Impedance85
Output Skew (ps)50
Output TypeLP-HCSL
Output Voltage (V)0.8V
Outputs (#)6
PLLYes
Package Area (mm²)25
Pitch (mm)0.4
Pkg. Dimensions (mm)5.0 x 5.0 x 0.9
Pkg. TypeVFQFPN
Power Consumption Typ (mW)149
Product CategoryPCI Express Clocks
Prog. ClockNo
Reference OutputNo
Spread SpectrumYes
Supply Voltage (V)3.3 - 3.3
Tape & ReelNo
Thickness (mm)0.9
Width (mm)5

Description

The 9DBL0651 6-output 3.3V PCIe zero-delay/fanout buffer supports PCIe Gen 1 through Gen 6 and both Common and Independent Reference Clock architectures.

For information regarding evaluation boards and material, please contact your local sales representative.

Learn more about 9DBL0651