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Overview

Description

The 9DB102 zero-delay buffer supports PCI Express clocking requirements. The 9DB102 is driven by a differential SRC output pair from an IDT CK409/CK410-compliant main clock generator such as the 952601 or 954101. It attenuates jitter on the input clock and has a selectable PLL Band Width to maximize performance in systems with or without Spread- Spectrum clocking.

Features

  • 2 - 0.7 V HCSL differential output pairs
  • Phase jitter: PCIe Gen2 < 3.1 ps rms
  • Phase jitter: PCIe Gen1 < 86 ps peak to peak
  • Supports zero delay buffer mode and fanout mode
  • Bandwidth programming available
  • 33-110 MHz operation in PLL mode
  • 10-110 MHz operation in Bypass mode

Comparison

Applications

Documentation

Design & Development

Models

ECAD Models

Schematic symbols, PCB footprints, and 3D CAD models from SamacSys can be found by clicking on the CAD Model links in the Product Options table. If a symbol or model isn't available, it can be requested directly from SamacSys.

Diagram of ECAD Models

Models

Type Title Date
Model - IBIS ZIP 11 KB
1 item

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Videos & Training

This is the first video in our PCIe series. In this video, we define PCIe architectures, focusing on common and separate clock architectures. Watch the rest of the video series below where Ron will cover the impact of different timing architectures.

Watch the Video Series Below