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Features

  • Feedback pins for input to output synchronization
  • Spread Spectrum tolerant inputs; 
  • Auto PD when input signal is at a certain logic state

Description

Low skew, low jitter PLL clock driver; 1 to 4 differential clock distribution (SSTL_18)

Part NumberStatusSamplesStockPackageLead Count (#)Temp. GradePb (Lead) FreeCarrier Type
97ULP844AHObsoleteN/AOut of StockCABGA28#CNoTray
97ULP844AHLFObsoleteN/AOut of StockCABGA28#CYesTray
97ULP844AHLFTObsoleteN/AOut of StockCABGA28#CYesReel
97ULP844AHTObsoleteN/AOut of StockCABGA28#CNoReel
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