Features
- Device clock domain (RF-PLL) with support for JESD204B/C
- Digital clock domain (Ethernet, FEC) with support for eEEC and T-BC/T-TSC Class C
- 2 differential clock reference inputs with 1PPS (1Hz) to 1GHz input frequency
- Dual DPLL front-end with independent clock paths
- External control of the DCO for IEEE1588
- Digital holdover with a 1.1 × 10-7 ppb accuracy
- Programmable DPLL loop bandwidth 1mHz - 6kHz
- Configurable phase delay (range: 1UI)
- Hitless input switching with < 1ns output phase error
- Reference monitors for input LOS, activity and frequency
- 1 external synchronization input for JESD204B/C (LVCMOS)
- 16 differential outputs
- Optimized for low phase noise: -146dBc/Hz (1MHz offset; 245.76MHz clock)
- Supply voltage (core): 3.3V; (outputs): 3.3V, 2.5V, and 1.8V
- Board temperature range: -40°C to +105°C
- Applicable Standards
- ITU-T G.8262 EEC1/2, G.8262.1 eEEC
- ITU-T G.8273.2 T-BC/T-TSC Class C
- JESD204B and C
Description
The 8V19N850 is a fully integrated Radio Unit Clock Synchronizer and Jitter Attenuator designed as a high-performance clock solution for phase/frequency synchronization and signal conditioning of wireless base station radio equipment. The device supports JESD204B/C subclass 0 and 1 device clocks and SYSREF synchronization for converters. The 8V19N850 supports two independent frequency domains: one that can be used for the digital clock (Ethernet and FEC rates) domain with four outputs, and the device clock (RF-PLL) domain with 12 outputs. The Ethernet domain generates frequencies from two independent APLLs for flexibility; the outputs of the RF clock domain generate very low phase noise clocks for ADC/DAC circuits.
From the integrated RF-PLL, the device supports the clock generation of high-frequency device clocks for driving ADC/DAC devices low-frequency synchronization signals (SYSREF). A dual DPLL front-end architecture supports any frequency translation. Each DPLL provides a programmable bandwidth and a DCO function for real-time frequency/phase adjustments. The DPLLs can lock on 1PPS input signals and establish lock within 100s or less. Frequency information can be applied from DPLL-0 to DPLL-1 and vice versa to enable the combining of the frequency characteristics of two references (combo-mode). The 8V19N850 is configured through a pin-mapped I3C (including legacy I2C) and 3/4-wire SPI interface. I2C with master capabilities reads a default configuration from an external ROM device. GPIO ports can be configured for reporting and controlling purposes.
Parameters
| Attributes | Value |
|---|---|
| Output Freq Range (MHz) | 1.0E-6 - 1000 |
| Accepts Spread Spec Input | No |
| Supply Voltage (V) | 3.3 - 3.3, 2.5 - 2.5, 1.8 - 1.8 |
| Output Type | LVDS, LVPECL, LVCMOS |
| Battery Backup | No |
| Battery Seal | No |
| CPU Supervisory Function POR | No |
| Crystal Frequency Trimming | No |
| Frequency Out Pin | No |
| Inputs (#) | 2 |
| Input Freq (MHz) | 1.0E-6 - 1000 |
| DPLL Channels (#) | 2 |
| JESD204B/C Compliant | Yes |
| Frequency Plan | 2500 / Output_Divider, 2949.12 / Output_Divider, 3670-3868 / Output_Divider |
| Adjustable Phase | Yes |
| Noise Floor (dBc/Hz) | -165 |
| Phase Noise Supports GSM | Yes |
| Synthesis Mode | Integer, Fractional |
| Input Ref. Divider Resolution (bits) | 3 |
| Feedback Divider Resolution (bits) | 32 |
| Output Divider Resolution (bits) | 7 |
| Input Redundancy | Input Monitor, Digital holdover, Hitless switch, Phase-slope limiting |
| Channels (#) | 1 |
| Additive Phase Jitter Typ RMS (fs) | 52 |
| Grade | 5G |
| Output Banks (#) | 8 |
| Core Voltage (V) | 1.8 |
| Output Voltage (V) | 1.8V, 2.5V, 3.3V |
| Product Category | JESD204B/C |
Package Options
| Pkg. Type | Pkg. Dimensions (mm) | Lead Count (#) | Pitch (mm) |
|---|---|---|---|
| VFQFPN | 10.0 x 10.0 x 0.9 | 88 | 0.4 |
Applications
- Wireless infrastructure 5G radio
This video introduces the industry’s first fully-integrated synchronizer for 5G enhanced common public radio interface (eCPRI) radio synchronization.
Events & Webinars
News & Blog Posts
Blog Post
Feb 1, 2022
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Support Communities
-
8V19N850 IBIS model
I am performing pre layout simulations for 8V19N850 device connected to one of Xilinx UltraScale+ devices. It looks that model consist buffer model only for VDDO_V=3.3V but there is a possibility to use different voltages like 1.8V. Is there any plan to release models for different ...
Mar 29, 2023 -
8V19N850 IBIS model
I am performing pre layout simulations for 8V19N850 device connected to one of Xilinx UltraScale+ devices. It looks that model consist buffer model only for VDDO_V=3.3V but there is a possibility to use different voltages like 1.8V. Is there any plan to release models for different ...
Mar 29, 2023
Support Communities
