Features
- Eight low skew, low additive jitter LVDS output pairs
- Two selectable, differential clock input pairs
- Differential PCLK, nPCLK pairs can accept the following differential input levels: LVDS, LVPECL
- Maximum input clock frequency: 2GHz (maximum)
- LVCMOS/LVTTL interface levels for the control input (input select)
- Output skew: 8ps (typical)
- Propagation delay: 255ps (typical)
- Low additive phase jitter, RMS; fREF = 156.25MHz, VPP = 1V, 10kHz to 20MHz: 65fs (typical)
- Maximum device current consumption (IDD): 170mA
- 2.5V supply voltage
- Lead-free (RoHS 6), 28-lead VFQFN packaging
- -40 °C to 85 °C ambient operating temperature
8SLVD1208I - Block Diagram
Description
The 8SLVD1208I is a high-performance differential LVDS fanout buffer. The device is designed for the fanout of high-frequency, very-low additive phase noise clock and data signals. The 8SLVD1208I is characterized to operate from a 2.5V power supply. Guaranteed output-to-output and part-to-part skew characteristics make the 8SLVD1208I ideal for those clock distribution applications demanding well-defined performance and repeatability. Two selectable differential inputs and eight low skew outputs are available. The integrated bias voltage reference enables easy interfacing of single-ended signals to the device inputs. The device is optimized for low power consumption and low additive phase noise.
For a 3.3V version of this device, please refer to the 8SLVD1208-33I.
| Part Number | Status | Samples | Longevity | Stock | Package | Budgetary Price (USD) | Lead Count (#) | Carrier Type | Moisture Sensitivity Level (MSL) | Qty. per Reel (#) | Qty. per Carrier (#) | Pb (Lead) Free | Pb Free Category | Temp. Range (°C) | Country of Assembly | Country of Wafer Fabrication |
|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|
| 8SLVD1208NBGI | NRND | N/A | 2040 Apr | In Stock | VFQFPN | 1ku | $3.03 | 28# | Tray | 1 | 0 | 490# | Yes | e3 Sn | -40 to 85°C | CHINA, TAIWAN | AUSTRIA |
| 8SLVD1208NBGI/W | NRND | N/A | 2040 Apr | In Stock | VFQFPN | 1ku | $3.03 | 28# | Reel | 1 | 2500# | 0 | Yes | e3 Sn | -40 to 85°C | CHINA, TAIWAN | AUSTRIA |
| 8SLVD1208NBGI8 | NRND | N/A | 2040 Apr | In Stock | VFQFPN | 1ku | $3.03 | 28# | Reel | 1 | 2500# | 0 | Yes | e3 Sn | -40 to 85°C | CHINA, TAIWAN | AUSTRIA |
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- Application NotePDF 170 KB 7WDXRDKU4E7E-5-57318 May 13, 2014
- Application NotePDF 495 KB 7WDXRDKU4E7E-5-57312 May 12, 2014
- Application NotePDF 442 KB 7WDXRDKU4E7E-5-57298 May 08, 2014
- Application NotePDF 120 KB 7WDXRDKU4E7E-5-57289 May 06, 2014
- Application NotePDF 180 KB 7WDXRDKU4E7E-5-57283 May 06, 2014
- Product Change NoticePDF 983 KB Jun 25, 2019
- Product BriefPDF 378 KB 7WDXRDKU4E7E-6-1169 Aug 14, 2012
- Product Change NoticePDF 583 KB 7WDXRDKU4E7E-5-61343 Dec 20, 2016
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- Application NotePDF 1.99 MB 7WDXRDKU4E7E-5-57242 Mar 01, 2022
- Application NotePDF 170 KB 7WDXRDKU4E7E-5-57318 May 13, 2014
- Application NotePDF 495 KB 7WDXRDKU4E7E-5-57312 May 12, 2014View More (10)
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- Product Change NoticePDF 983 KB Jun 25, 2019
- Product Change NoticePDF 583 KB 7WDXRDKU4E7E-5-61343 Dec 20, 2016
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- Product BriefPDF 378 KB 7WDXRDKU4E7E-6-1169 Aug 14, 2012
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Overview of IDT's 8LSVP (LVPECL) and 8SLVD (LVDS) families of low-jitter fanout buffers from IDT. Fanout buffers are a useful building block of many clock trees, providing signal buffering and multiple low-skew copies of the input signal. IDT's high-performance, low additive phase noise, differential clock fan-out buffers offer up to 2 GHz clock operation, low additive phase jitter (12kHz - 20MHz) of 50 to 100 femtoseconds RMS max, fast output rise & fall times (less than 150ps), and single and dual channel functions (dual: matched propagation delay). Presented by Baljit Chandhoke, Product Marketing Manager at Integrated Device Technology, Inc. To learn more about IDT's industry-leading portfolio of fanout buffers, visit Renesas's RF Buffer page.
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