Features
- Four LVPECL/ECL outputs
- IN, nIN input can accept the following differential input levels: LVPECL, LVDS, CML
- 50Ω internal input termination to VT
- Output frequency: 2.5GHz (maximum)
- Output skew: 30ps (maximum)
- Part-to-part skew: 150ps (maximum)
- Additive phase jitter, RMS: 0.02ps (typical)
- Propagation Delay: 425ps (maximum)
- LVPECL mode operating voltage supply range: VCC = 2.375V to 3.465V, VEE = 0V
- ECL mode operating voltage supply range: VCC = 0V, VEE = -3.465V to 2.375V
- -40°C to 85°C ambient operating temperature
- Available in lead-free (RoHS 6) package
8S58021I - Block Diagram
Description
The 8S58021I is a high speed 1-to-4 Differential-to-LVPECL/ECL Fanout Buffer. The 8S58021I is optimized for high speed and very low output skew, making it suitable for use in demanding applications such as SONET, 1 Gigabit and 10 Gigabit Ethernet, and Fibre Channel. The internally terminated differential input and VREF_AC pin allow other differential signal families such as LVDS, LVPECL and CML to be easily interfaced to the input with minimal use of external components. The 8S58021I is packaged in a small 3mm x 3mm 16-pin VFQFN package which makes it ideal for use in space-constrained applications.
Support Communities
Get quick technical support online from Renesas Engineering Community technical staff.
Knowledge Base
Browse our knowledge base for helpful articles, FAQs, and other useful resources.
