Package Information
| Lead Count (#) | 24 |
| Pkg. Code | PGG24 |
| Pitch (mm) | 0.65 |
| Pkg. Type | TSSOP |
| Pkg. Dimensions (mm) | 7.8 x 4.4 x 1.0 |
Environmental & Export Classifications
| Moisture Sensitivity Level (MSL) | 1 |
| Pb (Lead) Free | Yes |
| ECCN (US) | NLR |
| HTS (US) | 8542390001 |
Product Attributes
| Lead Count (#) | 24 |
| Carrier Type | Reel |
| Moisture Sensitivity Level (MSL) | 1 |
| Qty. per Reel (#) | 3000 |
| Qty. per Carrier (#) | 0 |
| Pb (Lead) Free | Yes |
| Pb Free Category | e3 Sn |
| Temp. Range | -40 to +85°C |
| Core Voltage (V) | 2.5, 3.3 |
| Divider Value | 1, 2 |
| Function | Buffer, Multiplexer |
| Input Freq (MHz) | 0 - 250 |
| Input Type | LVCMOS, LVPECL, LVDS, LVHSTL, SSTL, HCSL |
| Inputs (#) | 2 |
| Length (mm) | 7.8 |
| MOQ | 3000 |
| Output Banks (#) | 2 |
| Output Freq Range (MHz) | 0 - 250 |
| Output Skew (ps) | 105 |
| Output Type | LVCMOS |
| Output Voltage (V) | 1.8, 2.5, 3.3 |
| Outputs (#) | 8 |
| Package Area (mm²) | 34.3 |
| Pitch (mm) | 0.65 |
| Pkg. Dimensions (mm) | 7.8 x 4.4 x 1.0 |
| Pkg. Type | TSSOP |
| Reel Size (in) | 13 |
| Requires Terms and Conditions | Does not require acceptance of Terms and Conditions |
| Tape & Reel | Yes |
| Thickness (mm) | 1 |
| Width (mm) | 4.4 |
Description
The 87008I is a low skew, 1:8 LVCMOS/LVTTL Clock Generator. The device has 2 banks of 4 outputs and each bank can be independently selected for ÷1 or ÷2 frequency operation. Each bank also has its own power supply pins so that the banks can operate at the following different voltage levels: 3.3V, 2.5V, and 1.8V. The low impedance LVCMOS/ LVTTL outputs are designed to drive 50? series or parallel terminated transmission lines. The divide select inputs, DIV_SELA and DIV_SELB, control the output frequency of each bank. The output banks can be independently selected for ÷1 or ÷2 operation. The bank enable inputs, CLK_ENA and CLK_ENB, support enabling and disabling each bank of outputs individually. The CLK_ENA and CLK_ENB circuitry has a synchronizer to prevent runt pulses when enabling or disabling the clock outputs. The master reset input, nMR/OE, resets the ÷1/÷2 flip flops and also controls the active and high impedance states of all outputs. This pin has an internal pull-up resistor and is normally used only for test purposes or in systems which use low power modes. The 87008I is characterized to operate with the core at 3.3V or 2.5V and the banks at 3.3V, 2.5V, or 1.8V. Guaranteed bank, output, and part-to-part skew characteristics make the 87008I ideal for those clock applications demanding well-defined performance and repeatability.