Features
- High speed 4:1 differential multiplexer with a 1:2 fanout buffer
- Two differential LVPECL or LVDS output pairs
- Four selectable differential PCLKx, nPCLKx input pairs
- PCLKx, nPCLKx pairs can accept the following differential input levels: LVPECL, LVDS, CML, SSTL
- Maximum output frequency: 3GHz
- Translates any single ended input signal to LVPECL levels with resistor bias on nPCLKx input
- Part-to-part skew: 25ps (typical)
- Propagation delay: 555ps (typical)
- Additive phase jitter, RMS: 0.16ps (typical)
- Full 3.3V or 2.5V supply modes
- -40°C to 85°C ambient operating temperature
- Available in lead-free (RoHS 6) package
859S0412I - Block Diagram
Description
The 859S0412I is a 4:2 Differential-to-LVPECL/ LVDS Clock Multiplexer which can operate up to 3GHz. The 859S0412I has 4 selectable differential PCLKx/nPCLKx clock inputs. The PCLKx, nPCLKx input pairs can accept LVPECL, LVDS, CML or SSTL levels. The fully differential architecture and low propagation delay make it ideal for use in clock distribution circuits. The clock select pins have internal pulldown resistors. The CLK_SEL1 pin is the most significant bit and the binary number applied to the select pins will select the same numbered data input (i.e., 00 selects PCLK0, nPCLK0).
Support Communities
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VCC_TAP pin
Hello, Is it okay to power the VCC_TAP pin in any other way that is not mentioned in the datasheets of 859S0212I, 859S0412I and 859S0424I multiplexer ICs ? Regards
Mar 20, 2024
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