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8543

Obsolete

Low Skew,1-to-4 Differential-to-LVDS Fanout Buffer

NOTICE - The following device(s) are recommended alternatives:
8P34S1204 - 2:4 LVDS 1.8V/2.5V Fanout Buffer for 1PPS and High-Speed Clocks
Functional replacement

Overview

The 8543 is a low skew, high performance 1-to-4 Differential-to-LVDS Clock Fanout Buffer. Utilizing Low Voltage Differential Signaling (LVDS) the 8543 provides a low power, low noise, solution for distributing clock signals over controlled impedances of 100?. The 8543 has two selectable clock inputs. The CLK, nCLK pair can accept most standard differential input levels. The PCLK, nPCLK pair can accept LVPECL, CML, or SSTL input levels. The clock enable is internally synchronized to eliminate runt pulses on the outputs during asynchronous assertion/deassertion of the clock enable pin. Guaranteed output and part-to-part skew characteristics make the 8543 ideal for those applications demanding well defined performance and repeatability.

8543 - Block Diagram
8543 - Pinout
8543 - Block Diagram
8543 - Pinout
  • Four differential LVDS output pairs
  • Selectable differential CLK, nCLK or LVPECL clock inputs
  • CLK, nCLK pair can accept the following differential input levels: LVPECL, LVDS, LVHSTL, SSTL, HCSL
  • PCLK, nPCLK pair can accept the following differential input levels: LVPECL, CML, SSTL
  • Maximum output frequency: 800MHz
  • Translates any single-ended input signals to LVDS levels with resistor bias on nCLK input
  • Additive phase jitter, RMS: 0.164ps (typical)
  • Output skew: 40ps (maximum)
  • Part-to-part skew: 500ps (maximum)
  • Propagation delay: 2.6ns (maximum)
  • Full 3.3V supply mode
  • 0°C to 70°C ambient operating temperature
  • Available in both standard (RoHS 5) and lead-free (RoHS 6) packages

Documentation

Design & Development

ECAD Models

Schematic symbols, PCB footprints, and 3D CAD models from SamacSys can be found by clicking on the CAD Model links in the Product Options table. If a symbol or model isn't available, it can be requested directly from SamacSys.

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Diagram of ECAD Models

Models
Type Title Date
Model - IBIS
8543I IBIS Model
ZIP 13 KB
1 item

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Support Communities

  1. Unable to debug RZ sample app on custom hardware

    (Not sure if this post belongs here or in the RZ forum) I'm adapting the Renesas RZ RGA Sample app (R01AN2163EJ0210) to my custom hardware (built with a RZ/A1H chip). I have managed to import the DS-5 project into e2studio and build it successfully.  I ...

    Jun 30, 2017
  2. Retarget Keil5 project for DA14580 to DA14586

    Hi, I have a Keil5 project for DA14580 target. The base for this project is ble_app_peripheral example from SDK 5.0.2.1 Now I want to retarget this project to DA14586, since that is the recommended part. What is the best way to do this? Thanks.

    May 21, 2020
  3. not enough space

    hi dialog     I am using 14585 and now I have this problem：    .\out_DA14585\Objects\prox_reporter_585.axf: Error: L6221E: Execution region ER_NZI with Execution range [0x07fd53f0,0x07fd57fc) overlaps with Execution region RET_DATA with Execution range [0x07fd576c,0x07fd5fb4).   How to solve this problem？ thanks   The amount of ...

    May 14, 2020
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