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Features

  • Twenty four LVPECL outputs.
  • One differential clock input pair
  • Differential input clock (PCLK, nPCLK) can accept the following signaling levels: LVDS, LVPECL, CML
  • Maximum output frequency: 2GHz
  • Translates any single ended input signal to 3.3V, 2.5V LVPECL levels with resistor bias on nPCLK input
  • Output skew: 125ps (maximum)
  • Rise and Fall Time: 180ps (typical)
  • Additive phase jitter, RMS: 0.15ps (typical) @ 156.25MHz
  • Full 3.3V or 2.5V supply voltage
  • 0°C to 70°C ambient operating temperature
  • Available in lead-free (RoHS 6) package

Description

The 853S024 is a low skew, 1-to-24 Differential-to-3.3V, 2.5V LVPECL Fanout Buffer. The PCLK, nPCLK pair can accept most standard differential input levels. The 853S024 is characterized to operate from either a 3.3V or a 2.5V power supply. Guaranteed output skew characteristics make the 853S024 ideal for those clock distribution applications demanding well defined performance and repeatability.
Part NumberStatusSamplesStockPackageLead Count (#)Carrier TypeMoisture Sensitivity Level (MSL)Qty. per Reel (#)Qty. per Carrier (#)Pb (Lead) FreePb Free CategoryTemp. Range (°C)
853S024AYLFObsoleteN/AIn StockTQFP64#Tray30160#Yese3 Sn0 to 70°C
853S024AYLFTObsoleteN/AIn StockTQFP64#Reel3500#0Yese3 Sn0 to 70°C
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