Lead Count (#) | 52 |
Pkg. Type | TQFP |
Pkg. Code | PPG52 |
Pitch (mm) | 0.65 |
Pkg. Dimensions (mm) | 10.0 x 10.0 x 1.4 |
Pb (Lead) Free | Yes |
ECCN (US) | NLR |
HTS (US) | 8542390000 |
Moisture Sensitivity Level (MSL) | 3 |
Pkg. Type | TQFP |
Lead Count (#) | 52 |
Pb (Lead) Free | Yes |
Carrier Type | Tray |
Core Voltage (V) | 3.3 |
Function | Buffer, Multiplexer |
Input Freq (MHz) | 0 - 500 |
Input Type | CML, HCSL, HSTL, LVDS, LVPECL, SSTL |
Inputs (#) | 2 |
Length (mm) | 10.0 |
MOQ | 160 |
Moisture Sensitivity Level (MSL) | 3 |
Output Banks (#) | 1 |
Output Freq Range (MHz) | 0 - 500 |
Output Skew (ps) | 50 |
Output Type | LVPECL |
Output Voltage (V) | 3.3 |
Outputs (#) | 17 |
Package Area (mm²) | 100.0 |
Pb Free Category | e3 Sn |
Pitch (mm) | 0.65 |
Pkg. Dimensions (mm) | 10.0 x 10.0 x 1.4 |
Qty. per Carrier (#) | 160 |
Qty. per Reel (#) | 0 |
Requires Terms and Conditions | Does not require acceptance of Terms and Conditions |
Tape & Reel | No |
Temp. Range | 0 to 70°C |
Thickness (mm) | 1.4 |
Width (mm) | 10.0 |
The 8532AY-01 is a low skew, 1-to-17, Differential- to-3.3V LVPECL Fanout Buffer and a member of the family of High Performance Clock Solutions from ICS. The 8532AY-01 has two selectable clock inputs. The CLK, nCLK pair can accept most standard differential input levels. The PCLK, nPCLK pair can accept LVPECL, CML, or SSTL input levels. The clock enable is internally synchronized to eliminate runt pulses on the outputs during asynchronous assertion/deassertion of the clock enable pin. Guaranteed output and part-to-part skew characteristics make the 8532AY-01 ideal for those clock distribution applications demanding well defined performance and repeatability.