Features
- Twenty-one differential HCSL outputs
- Translates any differential input signal (LVPECL, LVHSTL, LVDS, HCSL) to HCSL levels without external bias networks
- Maximum output frequency: 250MHz
- Output skew: 395ps (maximum)
- Part-to-part skew: 335ps (maximum)
- Output drift: 140ps (maximum)
- VOH: 850mV (maximum)
- Full 3.3V supply voltage
- Available in lead-free (RoHS 6) packages
- 0°C to 70°C ambient operating temperature
851021 - Block Diagram
Description
The 851021 is a 1-to-21 Differential HCSL Fanout Buffer. The 851021 is designed to translate any differential signal levels to differential HCSL output levels. An external reference resistor is used to set the value of the current supplied to an external load/termination resistor. The load resistor value is chosen to equal the value of the characteristic line impedance of 50 ohms. The 851021 is characterized at an operating supply voltage of 3.3V. The differential HCSL outputs, accurate crossover voltage and duty cycle make the 851021 ideal for interfacing to PCI Express® and FBDIMM applications.
| Part Number | Status | Samples | Stock | Package | Lead Count (#) | Carrier Type | Moisture Sensitivity Level (MSL) | Qty. per Reel (#) | Qty. per Carrier (#) | Pb (Lead) Free | Pb Free Category | Temp. Range (°C) |
|---|---|---|---|---|---|---|---|---|---|---|---|---|
| 851021AYLF | Obsolete | N/A | In Stock | TQFP | 64# | Tray | 3 | 0 | 160# | Yes | e3 Sn | 0 to 70°C |
| 851021AYLFT | Obsolete | N/A | Out of Stock | TQFP | 64# | Reel | 3 | 500# | 0 | Yes | e3 Sn | 0 to 70°C |
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- Application NotePDF 170 KB 7WDXRDKU4E7E-5-57318 May 13, 2014
- Application NotePDF 1.9 MB 7WDXRDKU4E7E-5-57315 May 13, 2014
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- Application NotePDF 442 KB 7WDXRDKU4E7E-5-57298 May 08, 2014
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- Application NotePDF 180 KB 7WDXRDKU4E7E-5-57283 May 06, 2014
- End Of Life NoticePDF 606 KB 7WDXRDKU4E7E-5-62524 Nov 29, 2017
- Product BriefPDF 378 KB 7WDXRDKU4E7E-6-1169 Aug 14, 2012
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- Application NotePDF 1.99 MB 7WDXRDKU4E7E-5-57242 Mar 01, 2022
- Application NotePDF 170 KB 7WDXRDKU4E7E-5-57318 May 13, 2014
- Application NotePDF 1.9 MB 7WDXRDKU4E7E-5-57315 May 13, 2014View More (12)
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- End Of Life NoticePDF 606 KB 7WDXRDKU4E7E-5-62524 Nov 29, 2017
- End Of Life NoticePDF 599 KB 7WDXRDKU4E7E-5-61808 Aug 24, 2017
- Product Change NoticePDF 567 KB 7WDXRDKU4E7E-5-60948 Aug 26, 2016
- Product Change NoticePDF 34 KB 7WDXRDKU4E7E-5-57765 Sep 28, 2014
- Product Change NoticePDF 788 KB 7WDXRDKU4E7E-5-57463 Jul 07, 2014
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- Product BriefPDF 378 KB 7WDXRDKU4E7E-6-1169 Aug 14, 2012
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This is the first video in our PCIe series. In this video, we define PCIe architectures, focusing on common and separate clock architectures. Watch the rest of the video series below where Ron will cover the impact of different timing architectures.
In this episode, Ron Wade from IDT (acquired by Renesas) explains PCIe common clocking and its impact on timing solutions. Learn about using a single clock source, fan-out buffers, and the considerations for spread spectrum and non-spread spectrum clocking in PCIe systems.
In this video, we explore PCIe with separate reference clocks and the effects of clock selection. Learn how separate reference clocks work and their impact on system performance and stability.
This video provides a high-level overview of Separate Reference Clock with Independent Spread (SRIS) architectures for PCI Express systems, additional performance requirements that this clocking architecture imposes on the reference clocks, and some system implications encountered trying to implement the architecture.
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