Features
- One differential LVDS output pair
- Crystal oscillator interface designed for 18pF, 25MHz parallel resonant crystal
- VCO range: 490MHz - 680MHz
- RMS phase jitter at 100MHz (12kHz - 20MHz): 0.792ps (typical)
- RMS phase jitter at 125MHz (12kHz - 20MHz): 0.773ps (typical)
- Full 3.3V output supply mode
- PCI Express® (2.5 Gb/s) and Gen 2 (5 Gb/S) jitter compliant
- -40°C to 85°C ambient operating temperature
- Available in lead-free (RoHS 6) package
844201I-45 - Block Diagram
Description
The 844201I-45 is a PCI Express clock generator. The 844201I-45 can synthesize 100MHz or 125MHz reference clock frequencies with a 25MHz crystal. The 844201I-45 has excellent phase jitter performance and is packaged in a small 16-pin VFQFN, making it ideal for use in systems with limited board space.
| Part Number | Status | Samples | Stock | Package | Lead Count (#) | Carrier Type | Moisture Sensitivity Level (MSL) | Qty. per Reel (#) | Qty. per Carrier (#) | Pb (Lead) Free | Pb Free Category | Temp. Range (°C) |
|---|---|---|---|---|---|---|---|---|---|---|---|---|
| 844201BKI-45LF | Obsolete | N/A | Out of Stock | VFQFPN | 16# | Tray | 3 | 0 | 624# | Yes | e3 Sn | -40 to 85°C |
| 844201BKI-45LFT | Obsolete | N/A | Out of Stock | VFQFPN | 16# | Reel | 3 | 2500# | 0 | Yes | e3 Sn | -40 to 85°C |
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- Product Change NoticePDF 5.71 MB Jun 09, 2020
- Application NotePDF 1.9 MB 7WDXRDKU4E7E-5-57315 May 13, 2014
- Application NotePDF 495 KB 7WDXRDKU4E7E-5-57312 May 12, 2014
- Application NotePDF 442 KB 7WDXRDKU4E7E-5-57298 May 08, 2014
- Application NotePDF 115 KB 7WDXRDKU4E7E-5-57294 May 07, 2014
- Application NotePDF 133 KB 7WDXRDKU4E7E-5-57291 May 06, 2014
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Datasheets (1)
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- Application NotePDF 1.99 MB 7WDXRDKU4E7E-5-57242 Mar 01, 2022
Application Notes & White Papers (20)
- Product Change NoticePDF 5.71 MB Jun 09, 2020
- Product Change NoticePDF 5.61 MB Jan 08, 2020
- Product Change NoticePDF 983 KB Jun 25, 2019
Product Notices (PCN, EOL, etc) (8)
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This is the first video in our PCIe series. In this video, we define PCIe architectures, focusing on common and separate clock architectures. Watch the rest of the video series below where Ron will cover the impact of different timing architectures.
In this episode, Ron Wade from IDT (acquired by Renesas) explains PCIe common clocking and its impact on timing solutions. Learn about using a single clock source, fan-out buffers, and the considerations for spread spectrum and non-spread spectrum clocking in PCIe systems.
In this video, we explore PCIe with separate reference clocks and the effects of clock selection. Learn how separate reference clocks work and their impact on system performance and stability.
This video provides a high-level overview of Separate Reference Clock with Independent Spread (SRIS) architectures for PCI Express systems, additional performance requirements that this clocking architecture imposes on the reference clocks, and some system implications encountered trying to implement the architecture.
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