Features
- Four 0.7V current mode differential HCSL output pairs
- Crystal oscillator interface: 25MHz
- Output frequency: 100MHz
- RMS period jitter: 3ps (maximum)
- Output skew: 70ps (maximum)
- Cycle-to-cycle jitter: 35ps (maximum)
- I2C support with readback capabilities up to 400kHz
- Spread Spectrum for electromagnetic interference (EMI) reduction
- 3.3V operating supply mode
- -40°C to 85°C ambient operating temperature
- Available in lead-free (RoHS 6) package
Description
The 841S04I is a PLL-based clock generator specifically designed for PCI_Express™ Clock Generation applications. This device generates a 100MHz HCSL clock. The device offers a HCSL (Host Clock Signal Level) clock output from a clock input reference of 25MHz. The input reference may be derived from an external source or by the addition of a 25MHz crystal to the on-chip crystal oscillator. An external reference may be applied to the XTAL_IN pin with the XTAL_OUT pin left floating. The device offers spread spectrum clock output for reduced EMI applications. An I2C bus interface is used to enable or disable spread spectrum operation as well as select either a down spread value of -0.35% or -0.5%.
| Part Number | Status | Samples | Stock | Package | Lead Count (#) | Carrier Type | Moisture Sensitivity Level (MSL) | Qty. per Reel (#) | Qty. per Carrier (#) | Pb (Lead) Free | Pb Free Category | Temp. Range (°C) |
|---|---|---|---|---|---|---|---|---|---|---|---|---|
| 841S04CGILF | Obsolete | N/A | In Stock | TSSOP | 24# | Tube | 1 | 0 | 62# | Yes | e3 Sn | -40 to 85°C |
| 841S04CGILFT | Obsolete | N/A | In Stock | TSSOP | 24# | Reel | 1 | 3000# | 0 | Yes | e3 Sn | -40 to 85°C |
- Product Change NoticePDF 361 KB 7WDXRDKU4E7E-5-55130 Mar 24, 2013
- End Of Life NoticePDF 218 KB 7WDXRDKU4E7E-5-62868 Apr 26, 2018
- Product Change NoticePDF 611 KB 7WDXRDKU4E7E-5-60321 Apr 14, 2016
- Product Change NoticePDF 611 KB 7WDXRDKU4E7E-5-59927 Feb 15, 2016
- Product Change NoticePDF 596 KB 7WDXRDKU4E7E-5-59884 Jan 28, 2016
- Product Change NoticePDF 544 KB 7WDXRDKU4E7E-5-59710 Nov 13, 2015
- Product Change NoticePDF 95 KB 7WDXRDKU4E7E-5-59609 Oct 22, 2015
- Product Change NoticePDF 333 KB 7WDXRDKU4E7E-5-59608 Oct 22, 2015
- Product Change NoticePDF 50 KB 7WDXRDKU4E7E-5-59245 Jul 21, 2015
- Product Change NoticePDF 291 KB 7WDXRDKU4E7E-5-59244 Jul 21, 2015
- Product Change NoticePDF 439 KB 7WDXRDKU4E7E-5-56251 Oct 11, 2013
Recommended Documents (1)
Datasheets (1)
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- End Of Life NoticePDF 218 KB 7WDXRDKU4E7E-5-62868 Apr 26, 2018
- Product Change NoticePDF 611 KB 7WDXRDKU4E7E-5-60321 Apr 14, 2016
- Product Change NoticePDF 611 KB 7WDXRDKU4E7E-5-59927 Feb 15, 2016
- Product Change NoticePDF 596 KB 7WDXRDKU4E7E-5-59884 Jan 28, 2016
- Product Change NoticePDF 544 KB 7WDXRDKU4E7E-5-59710 Nov 13, 2015View More (12)
Product Notices (PCN, EOL, etc) (12)
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This is the first video in our PCIe series. In this video, we define PCIe architectures, focusing on common and separate clock architectures. Watch the rest of the video series below where Ron will cover the impact of different timing architectures.
In this episode, Ron Wade from IDT (acquired by Renesas) explains PCIe common clocking and its impact on timing solutions. Learn about using a single clock source, fan-out buffers, and the considerations for spread spectrum and non-spread spectrum clocking in PCIe systems.
In this video, we explore PCIe with separate reference clocks and the effects of clock selection. Learn how separate reference clocks work and their impact on system performance and stability.
This video provides a high-level overview of Separate Reference Clock with Independent Spread (SRIS) architectures for PCI Express systems, additional performance requirements that this clocking architecture imposes on the reference clocks, and some system implications encountered trying to implement the architecture.