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Renesas Electronics Corporation
Low Skew,1-to-4,Multiplexed Differential/LVCMOS-to-LVCMOS/LVTTL Fanout Buffer

Package Information

CAD Model:View CAD Model
Pkg. Type:TSSOP
Pkg. Code:PGG16
Lead Count (#):16
Pkg. Dimensions (mm):5.0 x 4.4 x 1.0
Pitch (mm):0.65

Environmental & Export Classifications

Moisture Sensitivity Level (MSL)1
Pb (Lead) FreeYes
ECCN (US)EAR99
HTS (US)8542.39.0090

Product Attributes

Lead Count (#)16
Carrier TypeTube
Moisture Sensitivity Level (MSL)1
Qty. per Reel (#)0
Qty. per Carrier (#)96
Pb (Lead) FreeYes
Pb Free Categorye3 Sn
Temp. Range (°C)-40 to 85°C
Additive Phase Jitter Typ RMS (fs)40
Additive Phase Jitter Typ RMS (ps)0.04
Core Voltage (V)3.3
FunctionBuffer, Multiplexer
Input Freq (MHz)350
Input TypeHCSL, HSTL, LVCMOS, LVDS, LVPECL, SSTL
Inputs (#)2
Length (mm)5
MOQ192
Output Banks (#)1
Output Freq Range (MHz)350
Output Skew (ps)40
Output TypeLVCMOS
Output Voltage (V)1.8V, 2.5V, 3.3V
Outputs (#)4
Package Area (mm²)22
Pitch (mm)0.65
Pkg. Dimensions (mm)5.0 x 4.4 x 1.0
Pkg. TypeTSSOP
Price (USD)$5.292
Product CategoryClock Buffers & Drivers, Clock Multiplexers
PublishedNo
Requires Terms and ConditionsDoes not require acceptance of Terms and Conditions
Tape & ReelNo
Thickness (mm)1
Width (mm)4.4

Description

The 8305I is a low skew, 1-to-4, Differential/LVCMOS-to- LVCMOS/LVTTL Fanout Buffer. The 8305I has selectable clock inputs that accept either differential or single ended input levels. The clock enable is internally synchronized to eliminate runt pulses on the outputs during asynchronous assertion/deassertion of the clock enable pin. Outputs are forced LOW when the clock is disabled. A separate output enable pin controls whether the outputs are in the active or high impedance state. Guaranteed output and part-to-part skew characteristics make the 8305I ideal for those applications demanding well defined performance and repeatability.