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Synchronization Management Unit (SMU) for IEEE 1588 and Synchronous Ethernet

Package Information

CAD Model:View CAD Model
Pkg. Type:VFQFPN
Pkg. Code:NLG72
Lead Count (#):72
Pkg. Dimensions (mm):10.0 x 10.0 x 1.0
Pitch (mm):0.5

Environmental & Export Classifications

Moisture Sensitivity Level (MSL)3
Pb (Lead) FreeYes
ECCN (US)EAR99
HTS (US)8542.39.0090

Product Attributes

Lead Count (#)72
Carrier TypeTray
Moisture Sensitivity Level (MSL)3
Qty. per Reel (#)0
Qty. per Carrier (#)168
Pb (Lead) FreeYes
Pb Free Categorye3 Sn
Temp. Range (°C)-40 to 85°C
Advanced FeaturesFull SETS (ITU-T G.8264), Hitless Reference Switching, Fractional-N Input Dividers, External Sync Input, External Feedback, DCO with Physical Layer Frequency Support, LOS Inputs
ApplicationSystem Synchronizer, IEEE 1588 Synthesizer
Channels (#)3
Clock SupportG.813, G.8262, GR-1244-CORE, GR-253-CORE, G.8273.2
Core Voltage (V)1.8
Diff. Inputs4
Diff. Outputs4
Input Freq (MHz)1.0E-6 - 650
Input Freq Range Type1PPS (1 Hz), TDM, DS1, E1, SONET/SDH, Ethernet, OTN, Sync Pulse
Input TypeLVCMOS, LVPECL, LVDS
Inputs (#)6
Length (mm)10
MOQ168
Output Freq Range (MHz)1.0E-6 - 650
Output Freq Range Type1PPS (1 Hz), TDM, DS1, E1, DS2, E3, DS3, 100BASE-T, STM-1/OC-3, STM-4/OC-12, 1000BASE-T/X, STM-16/OC-48
Output TypeLVCMOS, LVPECL, LVDS
Outputs (#)12
Package Area (mm²)100
Phase Jitter Typ RMS (ps)0.56
Pitch (mm)0.5
Pkg. Dimensions (mm)10.0 x 10.0 x 1.0
Pkg. TypeVFQFPN
Product CategoryIEEE 1588, Network Synchronization
PublishedNo
Requires Terms and ConditionsDoes not require acceptance of Terms and Conditions
Tape & ReelNo
Thickness (mm)1
Width (mm)10

Description

The 82P33814 Synchronization Management Unit (SMU) provides tools to manage timing references, clock sources and timing paths for IEEE 1588 and Synchronous Ethernet (SyncE) based clocks. The device supports up to three independent timing paths that control: IEEE 1588 clock synthesis; SyncE clock generation; and general purpose frequency translation.The device supports physical layer timing with Digital PLLs (DPLLs) and it supports packet based timing with Digitally Controlled Oscillators (DCOs). Input-to-input, input-to-output and output-to-output phase skew can all be precisely managed. The device outputs low-jitter clocks that can directly synchronize Ethernet interfaces; as well as SONET/SDH and PDH interfaces and IEEE 1588 Time Stamp Units (TSUs).