Features
- Fourth generation FemtoClock® NG technology
- Two LVPECL output pairs
- Each output supports independent frequency selection at 25MHz, 125MHz, 156.25MHz, and 312.5MHz
- Two differential inputs support the following input types: LVPECL, LVDS, LVHSTL, SSTL, HCSL
- Accepts input frequencies from 8kHz to 155.52MHz including 8kHz, 1.544MHz, 2.048MHz, 19.44MHz, 25MHz, 77.76MHz, 125MHz, and 155.52MHz
- Crystal interface optimized for a 27MHz, 10pF parallel resonant crystal
- Attenuates the phase jitter of the input clock by using a low-cost fundamental mode crystal
- Customized settings for jitter attenuation and reference tracking using an external loop filter connection
- FemtoClock NG frequency multiplier provides low jitter, high-frequency output
- Absolute pull range: ±100ppm
- Power supply noise rejection (PSNR): -95dB (typical)
- FemtoClock NG VCXO frequency: 2500MHz
- RMS phase jitter at 156.25MHz, using a 27MHz crystal (12kHz - 20MHz): 0.6ps (typical)
- RMS phase jitter at 125MHz, using a 27MHz crystal (12kHz - 20MHz): 0.63ps (typical)
- 3.3V supply voltage
- -40 °C to 85 °C ambient operating temperature
- Available in lead-free (RoHS 6) package
Description
The 813N252I-02 device uses Renesas' fourth generation FemtoClock® NG technology for optimal high clock frequency and low phase noise performance, combined with low power consumption and high power supply noise rejection. The 813N252DI-02 is a PLL-based synchronous multiplier optimized for PDH or SONET to Ethernet clock jitter attenuation and frequency translation.
The 813N252DI-02 is a fully integrated phase-locked loop utilizing a FemtoClock NG digital VCXO that provides the low jitter, high-frequency SONET/PDH output clock that easily meets OC-48 jitter requirements. This VCXO technology simplifies PLL design by replacing the pullable crystal requirement of analog VCXOs with a fixed 27MHz generator crystal. Jitter attenuation down to 10Hz is provided by an external loop filter. Pre-divider and output divider multiplication ratios are selected using device selection control pins. The multiplication ratios are optimized to support most common clock rates used in PDH, SONET, and Ethernet applications. The device requires the use of an external, inexpensive fundamental mode 27MHz crystal. The device is packaged in a space-saving 32-VFQFN package and supports the industrial temperature range.
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