Features
- Ideal for the following applications:
- Network switching
- Two level prioritization of parallel data
- Bidirectional data transfer
- Bus matching between 18 bit and 36 bit data paths
- Width expansion to 36 bit per package
- Depth expansion to 8,192 words per package
- 10ns read/write cycle time, 6.5ns access time
- IDT Standard or First Word Fall Through timing
- Single or double register buffered Empty and Full Flags
- Easily expandable in depth and width
- Asynchronous or coincident Read and Write clocks
- Async or sync programmable Almost Empty and Almost Full flags with default settings
- Half Full flag capability
- Available in 128-pin TQFP and 121 PBGA packages
- Industrial temperature range (–40C to +85C) is available
72845 - Block Diagram
Description
The 72845 is a 4K x 18 First-In, First-Out memory with clocked read and write controls. It is functionally equivalent to two 72245 FIFOs in a single package with all associated control, data, and flag lines assigned to independent pins and would be applicable for a wide variety of data buffering needs, such as optical disk controllers, Local Area Networks (LANs), and interprocessor communication. Each of the two FIFOs has an 18-bit input and output port. The Read Clock can be tied to the Write Clock for single clock operation or the two clocks can run asynchronous of one another for dual-clock operation.
Support Communities
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Switch the role between observer and peripheral dynamically
Hi， I have an scenario which need to switch the device role between observer and peripheral, because the device need to accept a connection and listen the broadcast packet both. Now I use a button to do the role switch. I have do the modification base on the ble_peripheral ...
Feb 6, 2017 -
P24 bank pins configuration issue in RZ-FIVE
Hello, We are configuring P24 bank pins for below interfaces and below is the dts configurations for the same. SCIF4:TX: P24_5 ALT5RX: P24_4 ALT5Below is the dts pinmux configuration: scif4_pins: scif4 { pinmux =
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