Features
- Optimal combination of large capacity, design flexibility and small footprint
- Ideal for prioritization, bidirectional, and width expansion applications
- 10 ns read/write cycle time
- Separate control lines and data lines for each FIFO
- Separate Empty, Full, Programmable Almost-Empty and Almost- Full flags for each FIFO
- Enable puts output data lines in high-impedance state
- Available in 64-pin TQFP and STQFP packages
- Industrial temperature range (–40C to +85C)
72831 - Block Diagram
Description
The 72831 is a 2K x 9 dual synchronous (clocked) FIFO. The device is functionally equivalent to two 72231 FIFOs in a single package with all associated control, data, and flag lines assigned to separate pins. Each of the two FIFOs has a 9-bit input data port and a 9-bit output data port. The Read Clock can be tied to the Write Clock for single clock operation or the two clocks can run asynchronous of one another for dual clock operation. The 72831 architecture lends itself to many flexible configurations such as: 2-level priority data buffering, Bidirectional operation, Width expansion and Depth expansion.
Support Communities
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power of Minimum system in active mode
HI！ Hardware system conditions: the smallest system, nothing more than other chips. Software system conditions: debug mode, active mode Average current: the average current is about 600uA, and the average current is about 20uA when the low power mode is turned on I would like to ask the DA14580 debugging ...
Jan 22, 2017
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