Features
- 10ns read/write cycle time (8ns access time)
- Fixed, low first word data latency time
- Auto power down minimizes standby power consumption
- Retransmit operation with fixed, low first word data latency time
- Empty, Full and Half-Full flags signal FIFO status
- Programmable Almost-Empty and Almost-Full flags
- Easily expandable in depth and width
- Independent Read and Write clocks (permit reading and writing simultaneously)
- Available in 64-pin TQFP and STQFP packages
- Industrial temperature range (–40C to +85C) is available
72255 - Block Diagram
Description
The 72255 is an 8K x 18 SuperSync FIFO memory with clocked read and write controls. The Frequency Select pin (FS) has been removed, thus it is no longer necessary to select which of the two clock inputs, RCLK or WCLK, is running at the higher frequency. SuperSync FIFOs are particularly appropriate for networking, video, telecommunications, data communications and other applications that need to buffer large amounts of data.
Support Communities
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AC/DC Isolated 40W LED driver solutions (36V @ 1.1A)
Our customer SCAELEC is working on a Street Lighting redesign and is very interested in the IW3620. Is there any EVB available to test the IC ? I cannot find any documentation about it. Thanks for your help Nicolas
Nov 25, 2016 -
Enabling interrupt in a non-IRQ pin.
Hi Team, My processor: RZG2N. I have to clarify one doubt. I have a RTC on my custom board based of RZG2N. The RTC gives an Interrupt request when som event happens such as Alarm, Event pin state change etc. The RTC interrupt is connected to processor pin D15 (AG1 ...
Apr 5, 2024
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