Skip to main content
Renesas Electronics Corporation - June is Pride Month, a month to raise awareness of the rights and the culture of the LGBTQ+ community

Features

  • 10 ns read/write cycle time
  • Read and Write Clocks can be asynchronous or coincidental
  • Dual-Ported zero fall-through time architecture
  • Empty and Full flags signal FIFO status
  • Almost-Empty and Almost-Full flags set to Empty+7 and Full-7, respectively
  • Output enable puts output data bus in high-impedance state
  • Available in 28-pin 300 mil plastic DIP
  • Industrial temperature range (–40C to +85C) is available

Description

The 72220 is a 1K x 8 SyncFIFO™ with clocked read and write controls. This FIFO is useful for a wide variety of data buffering needs, such as graphics, Local Area Networks (LANs), and interprocessor communication. It has 8-bit input and output ports. The Read Clock can be tied to the Write Clock for single clock operation or the two clocks can run asynchronous of one another for dual clock operation.

Part NumberStatusSamplesStockPackageLead Count (#)Temp. GradePb (Lead) FreeCarrier Type
72220L10TPObsoleteN/AOut of StockPDIP28#CNoTube
72220L10TPGObsoleteN/AOut of StockPDIP28#CYesTube
72220L15TPObsoleteN/AOut of StockPDIP28#CNoTube
72220L25TPObsoleteN/AOut of StockPDIP28#CNoTube

Support Communities

  1. [sdk5]problem about ext_sleep

    Background 1>project name: projects\target_apps\ble_examples\ble_app_profile 2>#undef CFG_DEVELOPMENT_DEBUG in da1458x_config_basic.h 3>for simplify the problem,comment the line ://#include "custs1.h" in user_profiles_config.h; 4>change value of app_default_sleep_mode ...

    Dec 7, 2015
Support Communities

Support Communities

Get quick technical support online from Renesas Engineering Community technical staff.
Browse Articles

Knowledge Base

Browse our knowledge base for helpful articles, FAQs, and other useful resources.
Submit a Ticket

Submit a Ticket

Need to ask a technical question or share confidential information?