Overview
Description
The IDT663 is a low cost Phase-Locked Loop (PLL) designed for clock synthesis and synchronization. Included on the chip are the phase detector, charge pump, Voltage Controlled Oscillator (VCO) and an output buffer. Through the use of external reference and VCO dividers (implemented with the IDT674-01, for example), the user can easily configure the device to lock to a wide variety of input frequencies. The phase detector and VCO functions of the device can also be used independently. This enables the configuration of other PLL circuits. For example, the IDT663 phase detector can be used to control a VCXO circuit such as the MK3754. For applications requiring Power Down or Output Enable features, please refer to the IDT673-01.
Features
- Packaged in 8-pin SOIC (Pb free)
- Output clock range 1 MHz to 100 MHz (3.3 V), 1 MHz to 120 MHz (5 V)
- External PLL loop filter enables configuration for a wide range of input frequencies
- Ability to accept an input clock in the kHz range (video HSYNCH, for example)
- 25 mA output drive capability at TTL levels
- Lower power CMOS process
- +3.3 V ±5% or +5 V ±10% operating voltage
- Used along with the IDT674-01, forms a complete PLL circuit
- Phase detector and VCO blocks can be used independently for other PLL configurations
- Industrial temperature version available
- For better jitter performance, use the MK1575
Comparison
Applications
Design & Development
Models
ECAD Models
Schematic symbols, PCB footprints, and 3D CAD models from SamacSys can be found by clicking on the CAD Model links in the Product Options table. If a symbol or model isn't available, it can be requested directly from SamacSys.
Support
Support Communities
Get quick technical support online from Renesas Engineering Community technical staff.
Support Communities
-
RX630 Bootloader function in RAM
Hi all I have a simple boot loader program that calls a delay function and toggles an output pin If i locate the delay function in data memory (RAM) the program fails to execute the delay and jumps to hex address 0x0000 If i locate the delay function in flash ...
Jun 14, 2016 -
e2studio and RH850_F1H
Hello all, I'm trying to get started with e2-studio for RH850_F1H using both cores. Have installed e2-studio 5.0.1.005. Unfortunatelly the tutorial of it (for Renesas toolchain) does not reflect what I get when using the tool in the described way. Is dual-core ...
Jun 14, 2016 -
Which Synergy example apps support SSP v1.1.0?
Here is a list of all Synergy example applications on the renesas.com website and which version of SSP they each support: Published Summary Website publication date Published SSP version Creating a BSP 16-Jan-12 1.0.0 GUIX Hello World SK-S7G2 16-Jan-22 1.0.0 ...
Jun 15, 2016