Features
- Packaged in 8-pin SOIC (Pb free)
- Output clock range 1 MHz to 100 MHz (3.3 V), 1 MHz to 120 MHz (5 V)
- External PLL loop filter enables configuration for a wide range of input frequencies
- Ability to accept an input clock in the kHz range (video HSYNCH, for example)
- 25 mA output drive capability at TTL levels
- Lower power CMOS process
- +3.3 V ±5% or +5 V ±10% operating voltage
- Used along with the IDT674-01, forms a complete PLL circuit
- Phase detector and VCO blocks can be used independently for other PLL configurations
- Industrial temperature version available
- For better jitter performance, use the MK1575
Description
The IDT663 is a low cost Phase-Locked Loop (PLL) designed for clock synthesis and synchronization. Included on the chip are the phase detector, charge pump, Voltage Controlled Oscillator (VCO) and an output buffer. Through the use of external reference and VCO dividers (implemented with the IDT674-01, for example), the user can easily configure the device to lock to a wide variety of input frequencies. The phase detector and VCO functions of the device can also be used independently. This enables the configuration of other PLL circuits. For example, the IDT663 phase detector can be used to control a VCXO circuit such as the MK3754. For applications requiring Power Down or Output Enable features, please refer to the IDT673-01.
Filters
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- Application NotePDF 187 KB R31AN0065EU0101 Rev.1.01 Nov 14, 2023
- Application NotePDF 1.99 MB 7WDXRDKU4E7E-5-57242 Mar 01, 2022
- Application NotePDF 170 KB 7WDXRDKU4E7E-5-57318 May 13, 2014
- Application NotePDF 495 KB 7WDXRDKU4E7E-5-57312 May 12, 2014
- Application NotePDF 442 KB 7WDXRDKU4E7E-5-57298 May 08, 2014
- Application NotePDF 115 KB 7WDXRDKU4E7E-5-57294 May 07, 2014
- Application NotePDF 136 KB 7WDXRDKU4E7E-5-57044 Mar 12, 2014
Recommended Documents (1)
Datasheets (1)
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- Application NotePDF 187 KB R31AN0065EU0101 Rev.1.01 Nov 14, 2023
- Application NotePDF 1.99 MB 7WDXRDKU4E7E-5-57242 Mar 01, 2022
Application Notes & White Papers (18)
- End Of Life NoticePDF 161 KB 7WDXRDKU4E7E-5-56346 Oct 29, 2013
- Product Change NoticePDF 439 KB 7WDXRDKU4E7E-5-56251 Oct 11, 2013
- Product Change NoticePDF 148 KB 7WDXRDKU4E7E-5-55894 Jul 29, 2013
- End Of Life NoticePDF 161 KB 7WDXRDKU4E7E-5-55879 Jul 25, 2013
- End Of Life NoticePDF 159 KB 7WDXRDKU4E7E-5-55231 Apr 10, 2013View More
Product Notices (PCN, EOL, etc) (6)
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Support Communities
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wear leveling in data flash
is there an application note or ducumentation and code that demonstrates how to use wear leveling??
Sep 25, 2009 -
Difference Between I2C and IICA
Hi all, Can anyone please tell me the difference between the I2C communication protocol and IICA communication protocol,?? Thank You
Jun 15, 2016 -
FSL library for IAR
Hi, i'm trying to write bootloaderfor RL78 microcontrollers from Example code - RL78/G13 Boot Loader through SCII migrated project and sources to IAR compiler. But can't use FSL.lib library. Is there another version of this library for IAR compiler?
Jun 15, 2016