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RZ/T1

Realize Real-Time Control of Industrial Equipment and Networking at the Same Time

 

The RZ/T1 Group has the ARM® Cortex®-R4 Processor with FPU core, which was designed for real-time processing, and is capable of high-speed operation at up to 600 MHz. Furthermore, access does not need to be performed via cache memory, and tightly-coupled memory capable of definitive real-time response processing is built-in, enabling high-speed access from the CPU without passing through the cache memory.

 

RZ/T1 devices that are equipped with a built-in R-IN engine, an accelerator for industrial Ethernet communications, can perform industrial Ethernet processing without loss of real-time performance.

 

Key Features :  RZ/T1(with R-IN engine)

ITEM RZ/T1(with R-IN engine)
Part NAME R7S910015 R7S910016 R7S910017 R7S910018
Packages 320FPBGA
0.8mm pitch
17mm x 17mm
Main CPU ARM® Cortex®-R4 Processor with FPU
Maximum operating frequency 450MHz 600MHz
FPU Supports single-precision and double-precision addition, subtraction, multiplication, division, multiply-accumulation, and square root calculation
Tightly-coupled memory ATCM: 512 KB (with ECC); BTCM: 32 KB (with ECC)
Cache memory Instruction cache: 8 KB (with ECC); data cache: 8 KB (with ECC)
Communication accelerator R-IN engine multi-protocol communication accelerator
Expanded internal SRAM 1 MB (with ECC) *also used for storing protocol stack
Clocks  External clock/resonator input frequency: 25 MHz
CPU clock frequency: up to 450/600 MHz
Low-speed on-chip oscillator (LOCO): 240 kHz
Timers Up to 33 expanded timer functions
16-bit TPUa (12 channels), MTU3a (9 channels), GPTa (4 channels): input capture, output compare, PWM waveform output
16-bit CMT (6 channels), 32-bit CMTW (2 channels)
*176-pin packages differ in number of channels, etc.
Communications EtherMAC: 1 port (with switching)
EtherCAT slave controller
USB 2.0 high-speed host/function: 1 channel
CAN (ISO 11898-1 compliant): up to 2 channels
16-byte SCIFA with FIFO: 5 channels
I2C bus interface: 2 channels of up to 400 kbps transfer speed
RSPIa: 4 channels
SPIBSC: 1 channel of multi-I/O serial flash memory connectable
Memory interfaces SPI 4ch
QSPI(Flash I/F) with Direct Access from CPU
SRAM I/F(32bit bus)
SDRAM I/F(32bit bus)
Burst ROM I/F(32bit bus)
Encoder
interfaces
-

A-format™,

BiSS-C,

EnDat2.2, Tamagawa

-

A-format™,

BiSS-C,

EnDat2.2, Tamagawa

A/D converter 12-bit A/D converter: 2 units (unit 0: 8 channels; unit 1: 16 channels)
DMA 16 channels x 2 units
Other functions Built-in temperature sensor for measuring internal chip temperature
Safety features (register write protection, input clock oscillation stop detection, CRC, IWDTa, A/D self-diagnostics, error control module, etc.)
Security functions (option): Secure boot, JTAG lock, etc.
Power supply voltage 3.3 V (I/O), 1.2 V (internal)
Operating temperature range Tj = -40℃ ~ +125℃

 

Key Features :   RZ/T1(without R-IN engine)

ITEM RZ/T1 (without R-IN engine)

Part

Name

R7S910001

R7S910002
R7S910011
R7S910006

R7S910007
R7S910013
R7S910025
R7S910026
R7S910027
R7S910028

R7S910035

R7S910036

Packages

176HLQFP
0.4mm pitch
20mm x 20mm

320FPBGA
0.8mm pitch
17mm x 17mm

Main CPU

ARM® Cortex®-R4 Processor with FPU

Maximum operating frequency

450MHz 600MHz 450MHz 600MHz 300MHz

FPU

Supports single-precision and double-precision addition, subtraction, multiplication, division, multiply-accumulation, and square root calculation

Tightly-

coupled

memory

ATCM: 512 KB (with ECC); BTCM: 32 KB (with ECC)

Cache

memory

Instruction cache: 8 KB (with ECC); data cache: 8 KB (with ECC)

Expanded internal

SRAM

- - 1MB (with ECC) 1MB(with ECC) -

Clocks

  • External clock/resonator input frequency: 25 MHz
  • CPU clock frequency: up to 300/450/600MHz
  • Low-speed on-chip oscillator (LOCO): 240 kHz

Timers

Up to 33 expanded timer functions
  • 16-bit TPUa (12 channels), MTU3a (9 channels), 
  • GPTa (4 channels): input capture, output compare, PWM waveform output
  • 16-bit CMT (6 channels), 32-bit CMTW (2 channels)

*176-pin packages differ in number of channels, etc.

Communi

cations

  • EtherMAC: 1 port (with switching)
  • USB 2.0 high-speed host/function: 1 channel
  • CAN (ISO 11898-1 compliant): up to 2 channels
  • 16-byte SCIFA with FIFO: 5 channels
  • I2C bus interface: 2 channels of up to 400 kbps transfer speed
  • RSPIa: 4 channels
  • SPIBSC: 1 channel of multi-I/O serial flash memory connectable

*176-pin packages differ in number of channels, ports, etc.

Memory interfaces

  • SPI 4ch
  • QSPI(Flash I/F) with Direct Access from CPU
  • SRAM I/F(32bit bus)
  • SDRAM I/F(32bit bus)
  • Burst ROM I/F(32bit bus)
EtherCAT
Slave Controller
- support

Encoder
interfaces

-

A-format™,

BiSS-C,

EnDat2.2, Tamagawa

 (R7S910011)

-

A-format™,

BiSS-C,

EnDat2.2, Tamagawa

(R7S910013)

A-format™,

BiSS-C,

EnDat2.2, Tamagawa

(R7S910026)

A-format™,

BiSS-C,

EnDat2.2, Tamagawa

 (R7S910028)

A-format™,

BiSS-C,

EnDat2.2, Tamagawa

(R7S910036)

A/D converter

12-bit A/D converter: 2 units (unit 0: 8 channels; unit 1: 16 channels)
*176-pin packages only have unit 0.
DMA 16 channels x 2 units
Other functions
  • Built-in temperature sensor for measuring internal chip temperature
  • Safety features
  • (register write protection, input clock oscillation stop detection, CRC, IWDTa,
  • A/D self-diagnostics, error control module, etc.)
  • Security functions (option): Secure boot, JTAG lock, etc.

Power supply voltage Operating

3.3 V (I/O), 1.2 V (internal)

temperature range

Tj = -40 to +125°C

 

Pin Count / Memory Size:

RZ/T1-Pin Count/Memory Size

Block Diagram:  

with R-IN engine

RZ/T1(with R-IN engine) Block Diagram

 

without R-IN engine

RZ/T1(without R-IN engine) Block Diagram

*ARM and Cortex are registered trademarks of ARM Limited (or its subsidiaries) in the EU and/or elsewhere.
All rights reserved.

*EtherCAT is a patented technology that Renesas has licensed from Beckhoff Automation GmbH, and is a registered trademark.

*EtherNet/IP is a trademark of ODVA.

*BiSS is a registered trademark of iC-Haus.

*CAN(Controller Area Network):An automotive network specification developed by Robert Bosch GmbH of Germany.

*All other names of products or services mentioned here are trademarks or registered trademarks of their respective owners.

* A-format is a trademark of the Nikon Corporation.

Below you will find information to support the development of your application.
You can find an explanation of orderable part numbers here.

 

Resources for Software and Hardware

Title Description
My Renesas Create a My Renesas account to use our tool download services, receive e-newsletter/update notifications, and take advantage of our other services.
e-learning Information for studying and learning about microcontrollers and microprocessors.
FAQ Frequently asked questions and useful hints for development.
Forum A forum and community site to share technical information, questions and opinions with others who use Renesas products.
Video Watch videos related to this product.

 

Resources for Software and Hardware

Title Description
Register definition To be able to use as specified variables, this iodefine.h is defined the peripheral I/O registers.

 

Resources for Software and Hardware

Title Description
Oscillation circuit characteristics
(Murata)

Search for part name starting with "R7S9100" (part name are listed on each product group page) on the oscillator manufacturer's Web site to check for supported oscillators. If you require optimal oscillation circuit constants for your particular system, please ask the manufacturer of the oscillator.

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