The Renesas 8P34S1106 is a high-performance differential LVDS fanout buffer. The device is designed for the fanout of high-frequency, very low additive phase-noise clock and data signals. The 8P34S1106 is characterized to operate from a 1.8V power supply. Guaranteed output-to-output and part-to-part skew characteristics make the 8P34S1106 ideal for those clock distribution applications demanding well-defined performance and repeatability. One differential input and six low skew outputs are available. The integrated bias voltage reference enables easy interfacing of AC-coupled signals to the differential device input. The device is optimized for low power consumption and low additive phase jitter.
Features
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Six low skew, low additive jitter LVDS output pairs
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One differential clock input pair
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Differential PCLK, nPCLK pair can accept the following differential input levels: LVDS, LVPECL, CML
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Maximum input clock frequency: 1.2GHz (maximum), design target
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Output skew: 20ps (typical)
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Propagation delay: 290ps (typical)
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Low additive phase jitter, RMS
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fREF = 156.25MHz, VPP = 1V, 12kHz–20MHz: 39fs (typical)
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Full 1.8V supply voltage
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Lead-free (RoHS 6), 20-VFQFPN packaging
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-40°C to 85°C ambient operating temperature