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Overview

Description

The 8P34S1106 is a high-performance differential LVDS fanout buffer. The device is designed for the fanout of high-frequency, very low additive phase noise clock and data signals. The 8P34S1106 is characterized to operate from a 1.8V power supply. Guaranteed output-to-output and part-to-part skew characteristics make the 8P34S1106 ideal for those clock distribution applications demanding well-defined performance and repeatability. One differential input and six low skew outputs are available. The integrated bias voltage reference enables easy interfacing of AC-coupled signals to the differential device input. The device is optimized for low power consumption and low additive phase jitter.

Features

  • Six low skew, low additive jitter LVDS output pairs
  • One differential clock input pair
  • Differential PCLK, nPCLK pair can accept the following differential input levels: LVDS, LVPECL, CML
  • Maximum input clock frequency: 1.2GHz (maximum), design target
  • Output skew: 20ps (typical)
  • Propagation delay: 290ps (typical)
  • Low additive phase jitter, RMS
  • fREF = 156.25MHz, VPP = 1V, 12kHz to 20MHz: 39fs (typical)
  • Full 1.8V supply voltage
  • Lead-free (RoHS 6), 20-VFQFPN packaging
  • -40 °C to 85 °C ambient operating temperature

Comparison

Applications

Documentation

Design & Development

Models

ECAD Models

Schematic symbols, PCB footprints, and 3D CAD models from SamacSys can be found by clicking on the CAD Model links in the Product Options table. If a symbol or model isn't available, it can be requested directly from SamacSys.

Diagram of ECAD Models

Models

Type Title Date
Model - IBIS ZIP 37 KB
1 item

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