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9DB633

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6-output 3.3 V PCIe Gen1-2-3 Zero Delay / Fanout Buffer

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Features

  • 6 - 0.7 V current mode differential HCSL output pairs
  • Cycle-to-cycle jitter < 50 ps
  • Output-to-output skew < 50 ps
  • PCIe Gen3 phase jitter < 1.0 ps RMS
  • OE# pins/Suitable for Express Card applications
  • PLL or bypass mode/PLL can dejitter incoming clock
  • Selectable PLL bandwidth/minimizes jitter peaking in downstream PLL's
  • Spread Spectrum Compatible/tracks spreading input clock for low EMI
  • SMBus Interface/unused outputs can be disabled
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9DB633 - Block Diagram
9DB633 - Pinout
9DB633 - Block Diagram
9DB633 - Pinout

Description

The 9DB633 zero-delay buffer supports PCIe Gen3 requirements, while being backwards compatible to PCIe Gen2 and Gen1. The 9DB633 is driven by a differential SRC output pair from an IDT 932S421 or 932SQ420 or equivalent main clock generator. It attenuates jitter on the input clock and has a selectable PLL bandwidth to maximize performance in systems with or without Spread-Spectrum clocking. An SMBus interface allows control of the PLL bandwidth and bypass options, while 2 clock request (OE#) pins make the 9DB633 suitable for Express Card applications.

Parameters

AttributesValue
Diff. Outputs6
Diff. Output SignalingHCSL
Output Freq Range (MHz)10 - 110
Diff. Inputs1
Diff. Input SignalingHCSL
Accepts Spread Spec InputYes
Power Consumption Typ (mW)442
Supply Voltage (V)3.3 - 3.3
Output TypeHCSL
Diff. Termination Resistors24
Package Area (mm²)42.7
Battery BackupNo
Battery SealNo
CPU Supervisory Function PORNo
Crystal Frequency TrimmingNo
Frequency Out PinNo
Inputs (#)1
Input Freq (MHz)100
FunctionZero Delay Buffer
Input TypeHCSL
Output Banks (#)1
Core Voltage (V)3.3
Output Voltage (V)3.3

Package Options

Pkg. TypePkg. Dimensions (mm)Lead Count (#)Pitch (mm)
TSSOP9.7 x 4.4 x 1.0280.65

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This is the first video in our PCIe series. In this video, we define PCIe architectures, focusing on common and separate clock architectures. Watch the rest of the video series below where Ron will cover the impact of different timing architectures.

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