Package Information
| CAD Model: | View CAD Model |
| Pkg. Type: | CFP |
| Pkg. Code: | KBT |
| Lead Count (#): | 16 |
| Pkg. Dimensions (mm): | 10.41 x 6.86 x 0.00 |
| Pitch (mm): | 1.27 |
Environmental & Export Classifications
| Moisture Sensitivity Level (MSL) | Not Applicable |
| Pb (Lead) Free | Exempt |
| ECCN (US) | 9A515.e.1 |
| HTS (US) | 8542.39.0090 |
Product Attributes
| Pkg. Type | CFP |
| Lead Count (#) | 16 |
| Carrier Type | Tray |
| Moisture Sensitivity Level (MSL) | Not Applicable |
| Qualification Level | Class Q |
| DLA SMD | 5962F9953602QXC |
| Pb (Lead) Free | Exempt |
| Pb Free Category | Gold Plate over compliant Undercoat-e4 |
| MOQ | 25 |
| Temp. Range (°C) | -55 to +125°C |
| CAGE code | 34371 |
| Bus Voltage (Max) (V) | 130 |
| DSEE (MeV·cm2/mg) | 90 |
| Die Sale Availability? | Yes |
| Driver Type | Half Bridge |
| Drivers (#) | 1 |
| FET Type | MOSFET |
| Fall Time | 60 |
| Flow | RH Hermetic |
| High Side Fall Time (max) (ns) | 40 |
| High Side Rise Time (max) (ns) | 40 |
| Input VCC (Max) (V) | 20 |
| Input VCC (Min) (V) | 12 |
| Length (mm) | 10.4 |
| Low Side Fall Time (max) (ns) | 40 |
| Low Side Rise Time (max) (ns) | 40 |
| Output Type | Synchronous |
| PROTO Availability? | Yes |
| Peak Output Current IPK (A) | 1.5 |
| Peak Output Sink Current (A) | 1.5 |
| Peak Output Source Current (A) | 1.5 |
| Pitch (mm) | 1.3 |
| Pkg. Dimensions (mm) | 10.4 x 6.9 x 0.00 |
| Rating | Space |
| Rise Time (Max) | 60 |
| SMD URL | 5962-99536 |
| TID HDR (krad(Si)) | 300 |
| Width (mm) | 6.9 |
Resources for IS-2100ARH
Description
The radiation hardened IS-2100ARH, IS-2100AEH are high-frequency, 130V half-bridge N-Channel MOSFET driver ICs, which are functionally similar to industry-standard 2110 types. The low-side and high-side gate drivers are independently controlled. This gives the user maximum flexibility in dead time selection and driver protocol. In addition, the devices have on-chip error detection and correction circuitry, which monitors the state of the high-side latch and compares it to the HIN signal. If they disagree, a set or reset pulse is generated to correct the high-side latch. This feature protects the high-side latch from single event upsets (SEUs).