Renesas’ Timing product portfolio has been acquired by SiTime.
Datasheets, documentation, and sample orders remain available on Renesas.com through late 2026. For new designs, purchasing, support, and product inquiries, visit SiTime.com or send an email to [email protected]. Full transition to SiTime is expected by late 2026.
| CAD Model: | View CAD Model |
| Pkg. Type: | VFQFPN |
| Pkg. Code: | NLG32 |
| Lead Count (#): | 32 |
| Pkg. Dimensions (mm): | 5.0 x 5.0 x 0.9 |
| Pitch (mm): | 0.5 |
| Pb (Lead) Free | Yes |
| ECCN (US) | EAR99 |
| HTS (US) | 8542.39.0090 |
| Moisture Sensitivity Level (MSL) | 3 |
| Pkg. Type | VFQFPN |
| Lead Count (#) | 32 |
| Pb (Lead) Free | Yes |
| Carrier Type | Tray |
| App Jitter Compliance | PCIe Gen1, PCIe Gen2 |
| C-C Jitter Max P-P (ps) | 85 |
| Chipset Manufacturer | Intel |
| Clock Spec. | CK505 |
| Core Voltage (V) | 3.3 |
| Die Form | No |
| Diff. Output Signaling | HCSL |
| Freq. Accuracy Init. (± PPM) | 100 |
| Input Freq (MHz) | 14.318 - 14.318 |
| Input Type | Crystal |
| Inputs (#) | 1 |
| Length (mm) | 5 |
| MOQ | 490 |
| Moisture Sensitivity Level (MSL) | 3 |
| Output Freq Range (MHz) | 14.318 - 14.318, 100 - 100, 133.33 - 133.33, 96 - 96, 120 - 120 |
| Output Signaling | HCSL |
| Output Skew (ps) | 100 |
| Output Type | HCSL, LVCMOS |
| Output Voltage (V) | 3.3V, 0.7V |
| Outputs (#) | 6 |
| PCIe Generation | Gen1, Gen2 |
| Package Area (mm²) | 25 |
| Pb Free Category | e3 Sn |
| Phase Jitter Max RMS (ps) | 3.1 |
| Pitch (mm) | 0.5 |
| Pkg. Dimensions (mm) | 5.0 x 5.0 x 0.9 |
| Qty. per Carrier (#) | 490 |
| Qty. per Reel (#) | 0 |
| Reference Output | Yes |
| Requires Terms and Conditions | Does not require acceptance of Terms and Conditions |
| Spread Spectrum | Yes |
| Supply Voltage (V) | 3.3 - 3.3 |
| Tape & Reel | No |
| Temp. Range (°C) | 0 to 70°C |
| Thickness (mm) | 0.9 |
| Width (mm) | 5 |
| Xtal Freq (MHz) | 14.318 - 14.318 |
| Xtal Inputs (#) | 1 |
CK505 clock, 32-pin applications.