Renesas’ Timing product portfolio has been acquired by SiTime.
Datasheets, documentation, and sample orders remain available on Renesas.com through late 2026. For new designs, purchasing, support, and product inquiries, visit SiTime.com or send an email to [email protected]. Full transition to SiTime is expected by late 2026.
| CAD Model: | View CAD Model |
| Pkg. Type: | TSSOP |
| Pkg. Code: | PGG28 |
| Lead Count (#): | 28 |
| Pkg. Dimensions (mm): | 9.7 x 4.4 x 1.0 |
| Pitch (mm): | 0.65 |
| Pb (Lead) Free | Yes |
| Moisture Sensitivity Level (MSL) | 1 |
| ECCN (US) | |
| HTS (US) |
| Pkg. Type | TSSOP |
| Lead Count (#) | 28 |
| Pb (Lead) Free | Yes |
| Carrier Type | Tube |
| Accepts Spread Spec Input | Yes |
| Advanced Features | HW PLL mode control |
| Architecture | Common,Data,Separate,Separate w/Spread |
| Chipset Manufacturer | Intel |
| Chipset Name | Lindenhurst, Twincastle |
| Core Voltage (V) | 3.3 |
| Diff. Input Signaling | HCSL |
| Diff. Inputs | 1 |
| Diff. Output Signaling | HCSL |
| Diff. Outputs | 4 |
| Diff. Termination Resistors | 16 |
| Input Freq (MHz) | 100 - 200 |
| Inputs (#) | 1 |
| Length (mm) | 9.7 |
| MOQ | 2000 |
| Moisture Sensitivity Level (MSL) | 1 |
| Multiplication Value | 1 |
| Output Banks (#) | 1 |
| Output Freq Range (MHz) | 80 - 220 |
| Output Skew (ps) | 50 |
| Output Type | HCSL |
| Output Voltage (V) | 0.8 |
| Outputs (#) | 4 |
| PLL | Yes |
| Package Area (mm²) | 42.7 |
| Pb Free Category | e3 Sn |
| Pitch (mm) | 0.65 |
| Pkg. Dimensions (mm) | 9.7 x 4.4 x 1.0 |
| Power Consumption Typ (mW) | 294 |
| Prog. Clock | No |
| Qty. per Carrier (#) | 50 |
| Qty. per Reel (#) | 0 |
| Requires Terms and Conditions | Does not require acceptance of Terms and Conditions |
| Supply Voltage (V) | 3.3 - 3.3 |
| Tape & Reel | No |
| Temp. Range (°C) | 0 to 70°C |
| Thickness (mm) | 1 |
| Width (mm) | 4.4 |
9DB104 is not recommended for new designs.