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Low Skew,1-to-2 LVCMOS/LVTTL-to-3.3V LVPECL Clock Generator

Package Information

CAD Model: View CAD Model
Pkg. Type: TSSOP
Pkg. Code: PGG14
Lead Count (#): 14
Pkg. Dimensions (mm): 5.0 x 4.4 x 1.0
Pitch (mm): 0.65

Environmental & Export Classifications

Moisture Sensitivity Level (MSL) 1
Pb (Lead) Free Yes
ECCN (US) EAR99
HTS (US) 8542.39.0090

Product Attributes

Lead Count (#) 14
Carrier Type Reel
Moisture Sensitivity Level (MSL) 1
Qty. per Reel (#) 2500
Qty. per Carrier (#) 0
Pb (Lead) Free Yes
Pb Free Category e3 Sn
Temp. Range (°C) -40 to 85°C
Additive Phase Jitter Typ RMS (fs) 30
Additive Phase Jitter Typ RMS (ps) 0.03
Core Voltage (V) 3.3
Function Buffer, Multiplexer
Input Freq (MHz) 266
Input Type LVCMOS
Inputs (#) 2
Length (mm) 5
MOQ 2500
Output Banks (#) 1
Output Freq Range (MHz) 266
Output Skew (ps) 20
Output Type LVPECL
Output Voltage (V) 3.3
Outputs (#) 2
Package Area (mm²) 22
Pitch (mm) 0.65
Pkg. Dimensions (mm) 5.0 x 4.4 x 1.0
Pkg. Type TSSOP
Published No
Reel Size (in) 13
Requires Terms and Conditions Does not require acceptance of Terms and Conditions
Tape & Reel Yes
Thickness (mm) 1
Width (mm) 4.4

Description

The 8535I-21 is a low skew, high performance 1-to-2 LVCMOS/LVTTL-to-3.3V LVPECL fanout buffer and a member of the HiPerClockS™ family of High Performance Clock Solutions from IDT. The 8535I-21 has two single-ended clock inputs. The single-ended clock input accepts LVCMOS or LVTTL input levels and translate them to 3.3V LVPECL levels. The clock enable is internally synchronized to eliminate runt clock pulses on the output during asynchronous assertion/deassertion of the clock enable pin. Guaranteed output and part-to-part skew characteristics make the 8535I-21 ideal for those applications demanding well defined performance and repeatability.